Freescale-semiconductor POWERPC MPC860T Manual do Utilizador descarregar pdf (Página 13)

MOTOROLA

Chapter 1. Overview

1-3

PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE

management of transmit and receive buffer memory

¥ 10/100 base-T media access control (MAC) features

Ñ Address recognition for broadcast, single station address, promiscuous mode,

and multicast hashing

Ñ Full support of media-independent interface (MII)

Ñ Interrupts supported per frame or per buffer (selectable buffer interrupt

functionality using the I bit is not supported however.)

Ñ Automatic interrupt vector generation for receive and transmit events (Tx

interrupts, Rx interrupts, and non-time critical interrupts)

Ñ Ethernet channel uses DMA burst transactions to transfer data to and from

external memory

1.4.1 MPC860TBlock Diagram

The FEC, the embedded PowerPC core, the system interface unit (SIU), and the

communication processor module (CPM) all use the 32-bit internal bus in an

MPC860Timplementation. Figure 1-1 is a block diagram of the MPC860T. For

information on the other modules, refer to the

MPC860T UserÕs Manual

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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Freescale-semiconductor POWERPC MPC860T Manual do Utilizador Página 13