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Overview

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

1-6 Freescale Semiconductor

— Supports the I

O standard

— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0

August 3, 1998)

— Support for 66 MHz, 3.3 V specification

— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port

— Makes use of the local bus signals, so there is no need for additional pins

1.2 Architecture Overview

The PowerQUICC II has two external buses to accommodate bandwidth requirements from the high-speed

system core and the very fast communications channels. As shown in Figure 1-1, the PowerQUICC II has

three major functional blocks:

• A 64-bit G2 core derived from the MPC603e with MMUs and cache

• A system interface unit (SIU)

• A communications processor module (CPM)

Figure 1-1 shows the block diagram of the superset PowerQUICC II device. Features that are device- or

silicon-specific are noted.

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