Freescale-semiconductor MPC8260 Manual do Utilizador

MPC8260 PowerQUICC™ IIFamily Reference ManualSupportsMPC8250MPC8255MPC8260MPC8264MPC8265MPC8266MPC8260RMRev. 2, 12/2005

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2viii Freescale Semiconductor ContentsParagraphNumber TitlePageNumber4.3.1.7 SIU External Interrup

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-6 Freescale Semiconductor — Supports the I2O standard— Hot-Swap friendly (supports the

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-80 Freescale Semiconductor 30.10.5.14 AAL2 TxBDsRefer t

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-81 30.10.7 UNI Statistics Table

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-82 Freescale Semiconductor the queue. If the CP tries t

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-83 30.11.3 Interrupt Queue Para

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-84 Freescale Semiconductor 30.12 The UTOPIA InterfaceTh

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-85 30.12.1.1 UTOPIA Master Mult

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-86 Freescale Semiconductor 30.12.2 UTOPIA Interface Sla

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-87 30.12.2.1 UTOPIA Slave Multi

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-88 Freescale Semiconductor 30.13.1 General FCC Mode Reg

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-89 8 ICD Idle cells discard0 D

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-7 Figure 1-1. PowerQUICC II Block DiagramBoth the system core a

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-90 Freescale Semiconductor 30.13.3 ATM Event Register (

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-91 Table 30-48 describes FCCE f

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-92 Freescale Semiconductor The first four PHY devices (

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-93 Example:Suppose the PowerQUI

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-94 Freescale Semiconductor 30.15 SRTS Generation and Cl

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-95 samples a new SRTS and store

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-96 Freescale Semiconductor For example, suppose a syste

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-1 Chapter 31 ATM AAL1 Circuit Emulation ServiceNOTEThe functionality

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-2 Freescale Semiconductor – Segment PDU directly from extern

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-3 31.2 AAL1 CES Transmitter Overview

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-8 Freescale Semiconductor The G2 core has an internal common on-chip (COP) debug proces

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-4 Freescale Semiconductor Section 31.4.6, “Channel Associate

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-5 received octet becomes the first b

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-6 Freescale Semiconductor Figure 31-4. AAL1 CES Receiver Dat

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-7 ATM receiver, set RCT[INVE] of the

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-8 Freescale Semiconductor In order to prevent an overrun con

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-9 and CESAC reaches the ATM_Start th

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-10 Freescale Semiconductor 31.4.5 Trunk ConditionAccording t

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-11 Figure 31-8. Internal CAS Block F

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-12 Freescale Semiconductor Figure 31-9. Mapping CAS Entry31

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-13 Table 31-1 describes CAS routing

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-9 1.2.3 Communications Processor Module (CPM)The CPM contains f

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-14 Freescale Semiconductor The user may use external logic t

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-15 the external framer. Each byte in

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-16 Freescale Semiconductor Mode.” In the example shown in Fi

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-17 Table 31-2 describes CES adaptive

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-18 Freescale Semiconductor Figure 31-16. Pre-Underrun Sequen

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-19 Figure 31-17. Pre-Overrun Sequenc

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-20 Freescale Semiconductor 31.6 3-Step-SN AlgorithmThe 3-ste

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-21 Figure 31-19. 3-Step-SN-Algorithm

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-22 Freescale Semiconductor Figure 31-20. Pointer verificatio

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-23 0x44 UDC_TMP_BASE Hword UDC mode

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-10 Freescale Semiconductor PowerQUICC II initialization code requires changes from the

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-24 Freescale Semiconductor 0x82 VCI_Filtering Hword VCI filt

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-25 Additional CES parameters needed

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-26 Freescale Semiconductor between transmit and receive conn

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-27 Table 31-5. RCT Field Description

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-28 Freescale Semiconductor 31.9.1.1 AAL1 CES Protocol-Specif

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-29 Table 31-6 describes AAL1 CES pro

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-30 Freescale Semiconductor 0x12 0 SPV Structured pointer val

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-31 31.9.2 Transmit Connection Table

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-32 Freescale Semiconductor Table 31-7. TCT Field Description

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-33 0x02 0-12 — Reserved, should be c

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-11 Figure 1-2. PowerQUICC II External SignalsVCCSYN/GNDSYN/VCCS

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-34 Freescale Semiconductor 31.9.2.1 AAL1 CES Protocol-Specif

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-35 31.10 Outgoing CAS Status Registe

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-36 Freescale Semiconductor 31.11 Buffer DescriptorsThe AAL1

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-37 Figure 31-26. Transmit Buffers an

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-38 Freescale Semiconductor Figure 31-27. Receive Buffers and

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-39 Table 31-11 describes AAL1 CES Rx

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-40 Freescale Semiconductor 31.12.2 AAL1 CES TxBDsFigure 31-2

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-41 31.13 AAL1 CES ExceptionsThere ar

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-42 Freescale Semiconductor 31.14 AAL1 Sequence Number (SN) P

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-43 31.15 Internal AAL1 CES Statisti

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-12 Freescale Semiconductor 1.4 Differences between MPC860 and PowerQUICC II The followi

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-44 Freescale Semiconductor 31.16 External AAL1 CES Statistic

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 31-45 The external framer then places t

ATM AAL1 Circuit Emulation ServiceMPC8260 PowerQUICC II Family Reference Manual, Rev. 231-46 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-1 Chapter 32 ATM AAL2NOTEThe functionality described in this chapter

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-2 Freescale Semiconductor AAL2 is subdivided into two sublayers, as shown in Figure 32

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-3 Figure 32-3. AAL2 Switching Example32.2 FeaturesThe PowerQUI

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-4 Freescale Semiconductor — A separate queue for every VP | VC | CID or a common queue

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-5 32.3 AAL2 TransmitterThe following sections describe the AAL

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-6 Freescale Semiconductor • Round robin (TCT[Fix]=0)• Fixed priority (TCT[Fix]=1)The f

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-7 Figure 32-5. Fixed Priority ModeThe TCT[OneP] determines the

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-13 1.6 PowerQUICC II ConfigurationsThe PowerQUICC II offers fle

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-8 Freescale Semiconductor 32.3.4 No STF ModeThe no-STF (no start of frame) mode enable

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-9 32.3.5.1 AAL2 Protocol-Specific TCTThe transmit connection t

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-10 Freescale Semiconductor .

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-11 Table 32-1. AAL2 Protocol-Specific Transmit Connection Tabl

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-12 Freescale Semiconductor 0x02 0-11 — Reserved, should be cleared during initializati

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-13 32.3.5.2 CPS Tx Queue DescriptorEach CPS TxBD table is mana

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-14 Freescale Semiconductor Table 32-2 describes the CPS TxQD fields..0 7 8 9 10 11 12

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-15 32.3.5.3 CPS Buffer StructureThe CPS buffer structure consi

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-16 Freescale Semiconductor Table 32-3 describes the CPS TxBD fields..0 1 2 3 4 7 8 15O

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-17 32.3.5.4 SSSAR Tx Queue DescriptorA SSSAR TxBD table and it

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-14 Freescale Semiconductor Table 1-3 shows serial performance for the MPC8250, which do

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-18 Freescale Semiconductor .Table 32-4. SSSAR TxQD Field DescriptionsOffset Bits Name1

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-19 32.3.5.5 SSSAR Transmit Buffer DescriptorThe SSSAR buffer s

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-20 Freescale Semiconductor 32.4 AAL2 ReceiverThe following sections describe the AAL2

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-21 The receiver issues an interrupt for each of the above erro

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-22 Freescale Semiconductor • RxQD offsets from 8 through 511 point into the internal R

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-23 Figure 32-14. AAL2 SwitchingA partial packet discard mode i

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-24 Freescale Semiconductor 32.4.4.1 AAL2 Protocol-Specific RCTThe receive connection t

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-25 Table 32-6. AAL2 Protocol-Specific RCT Field DescriptionsOf

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-26 Freescale Semiconductor 0x04 — — Reserved, should be cleared during initialization

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-27 32.4.4.2 CID Mapping Tables and RxQDsEach PHY | VP | VC | C

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-15 Figure 1-3. Remote Access Server ConfigurationIn this applic

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-28 Freescale Semiconductor 32.4.4.4 CPS Receive Buffer Descriptor (RxBD)The CPS RxBD s

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-29 .32.4.4.5 CPS Switch Rx Queue DescriptorThe switch RxQD, sh

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-30 Freescale Semiconductor Table 32-9 describes the CPS switch RxQD fields.32.4.4.6 SW

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-31 32.4.4.7 SSSAR Rx Queue DescriptorThe SSSAR RxQD, as shown

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-32 Freescale Semiconductor Table 32-11 describes the SSSAR RxQD fields..0 10 11 12 13

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-33 32.4.4.8 SSSAR Receive Buffer DescriptorThe SSSAR SDU is st

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-34 Freescale Semiconductor Table 32-12. SSSAR RxBD Field DescriptionsOffset Bits Name1

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-35 32.5 AAL2 Parameter RAMWhen configured for ATM mode, the FC

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-36 Freescale Semiconductor 0x62 APCP_BASE Hword APC parameters table base address. Use

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-37 0xA4 EPAYLOAD Word Reserved payload. Initialize to 0x6A6A6A

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor ix ContentsParagraphNumber TitlePageNumber5.4.2.2 Single PowerQUICC II Co

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-16 Freescale Semiconductor 1.7.1.2 Regional Office RouterFigure 1-4 shows a regional of

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-38 Freescale Semiconductor 32.6 User-Defined Cells in AAL2The user-defined cell (UDC)

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 32-39 Table 32-14 describes the interrupt queue entry fields for

ATM AAL2MPC8260 PowerQUICC II Family Reference Manual, Rev. 232-40 Freescale Semiconductor Table 32-15. AAL2 Interrupt Queue Entry CID = 0 Field Descr

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-1 Chapter 33 Inverse Multiplexing for ATM (IMA) NOTEThe functionality

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-2 Freescale Semiconductor IThe PowerQUICC II’s IMA microcode

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-3 — Discards cells with bad HECs (av

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-4 Freescale Semiconductor (2) can be programmed not to scree

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-5 Figure 33-1. Basic Concept of IMAI

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-6 Freescale Semiconductor Figure 33-2. Illustration of IMA F

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-7 33.2.3 Overview of IMA CellsAn IMA

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-17 Figure 1-5. LAN-to-WAN Bridge Router Configuration1.7.1.4 Ce

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-8 Freescale Semiconductor ATM RX FunctionCell 1Cell 2 Cell 3

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-9 ATM RX FunctionCell 1Cell 2 Cell 3

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-10 Freescale Semiconductor Figure 33-4. IMA Frame and ICP Ce

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-11 33.3.1.1 User Plane Functions Per

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-12 Freescale Semiconductor Figure 33-5. IMA Transmit Task In

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-13 At startup, the non-TRL links wil

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-14 Freescale Semiconductor At group start-up, instead of acc

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-15 Figure 33-8. Transmit Queue Behav

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-16 Freescale Semiconductor Figure 33-9. Transmit Queue Behav

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-17 2. The non-TRL tasks do not deter

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-18 Freescale Semiconductor Here the PowerQUICC II channelizes two E1s (up to 256, 16-Kb

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-18 Freescale Semiconductor received cells (and other event i

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-19 Cell Reception Task- Each IMA Lin

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-20 Freescale Semiconductor

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-21 Figure 33-11. IMA Microcode: Rece

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-22 Freescale Semiconductor The states are described as follo

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-23 • The system is only capable of c

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-24 Freescale Semiconductor available in its delay compensati

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-25 Figure 33-12. IMA Root Table Data

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-26 Freescale Semiconductor 33.4.2 IMA FCC Programming33.4.2.

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-27 NOTEIMAROOT must be programmed to

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-19 Figure 1-8. SONET Transmission Controller ConfigurationIn th

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-28 Freescale Semiconductor 0x3C TXPHYEN Word Transmit PHY en

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-29 33.4.3.1 IMA Control (IMACNTL)The

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-30 Freescale Semiconductor 33.4.4.1 IMA Group Transmit Table

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-31 33.4.4.1.1 IMA Group Transmit Con

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-32 Freescale Semiconductor Table 33-7 describes the IGTSTATE

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-33 33.4.4.1.4 ICP Cell TemplatesThe

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-34 Freescale Semiconductor 0x08 GROUP STATUS AND CONTROLByte

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-35 0x18 LINK 11 INFO Byte Status and

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-36 Freescale Semiconductor 33.4.4.2 IMA Group Receive Table

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-37 0x16 TRLR Hword TRL rate. Used on

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-20 Freescale Semiconductor core. The CP can store large data frames in the local memory

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-38 Freescale Semiconductor 33.4.4.2.1 IMA Group Receive Cont

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-39 33.4.4.2.2 IMA Group Receive Stat

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-40 Freescale Semiconductor Table 33-13 describes the IRGFS b

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-41 33.4.5 IMA Link TablesThe IMA lin

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-42 Freescale Semiconductor 33.4.5.1.1 IMA Link Transmit Cont

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-43 33.4.5.1.2 IMA Link Transmit Stat

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-44 Freescale Semiconductor Table 33-18 describes the ITINTST

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-45 0x07 DFC Byte Number of frames to

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-46 Freescale Semiconductor 33.4.5.2.1 IMA Link Receive Contr

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-47 33.4.5.2.2 IMA Link Receive State

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-21 Serial throughput is enhanced by connecting one PowerQUICC I

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-48 Freescale Semiconductor 33.4.5.3 IMA Link Receive Statist

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-49 33.4.6.2 Delay Compensation Buffe

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-50 Freescale Semiconductor IMA events sent to this queue inc

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-51 33.4.7.2 ICP Cell Reception Excep

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-52 Freescale Semiconductor 33.4.8 IDCR Timer ProgrammingProg

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-53 33.4.8.2.2 Programming the FCC P

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-54 Freescale Semiconductor 33.4.8.3 IDCR_Init CommandThe IDC

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-55 33.4.8.6 IDCR Counter AlgorithmTh

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-56 Freescale Semiconductor 33.4.9 APC Programming for IMADyn

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-57 Per the above explanation and exa

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-22 Freescale Semiconductor Figure 1-12. PCI ConfigurationIn this system the local bus i

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-58 Freescale Semiconductor 33.4.10 Changing IMA VersionA new

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-59 Figure 33-32. IMA Microcode/Softw

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-60 Freescale Semiconductor 33.5.3.2 General Operation• React

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-61 33.5.3.6 Transmit Group State Mac

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-62 Freescale Semiconductor 33.5.3.11 Test Pattern Control• I

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-63 of ICP cells requires that the co

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-64 Freescale Semiconductor • Set IGRSTATE[GDSS] to 1 (one) t

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-65 Figure 33-33. Near-End versus Far

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-66 Freescale Semiconductor 2. Assign corresponding group num

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-67 5. Program the Link’s ID (LID) in

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-23 to store ATM connection tables. Therefore, an external PCI b

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-68 Freescale Semiconductor 8. Inhibit reception of cells ove

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-69 5. Indicate that the link should

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-70 Freescale Semiconductor 33.5.4.9 Transmit Event Response

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-71 4. GDS (Group Delay Synchronized)

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-72 Freescale Semiconductor 33.5.4.11 Test Pattern ProcedureT

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-73 for the first link encountered in

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-74 Freescale Semiconductor 9. Program to appropriate rate an

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 33-75 33.5.4.13.2 ReceiveNo special fac

Inverse Multiplexing for ATM (IMA)MPC8260 PowerQUICC II Family Reference Manual, Rev. 233-76 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 34-1 Chapter 34 ATM Transmission Convergence LayerNOTEThe functionality

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-24 Freescale Semiconductor

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 234-2 Freescale Semiconductor — Protocol-specific overhead bits

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 34-3 • Cell counters for performance mo

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 234-4 Freescale Semiconductor Figure 34-2. TC Layer Block Diagra

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 34-5 SYNCH state, the TC is assumed to

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 234-6 Freescale Semiconductor Figure 34-4. HEC: Receiver Modes o

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 34-7 The FIFO management includes empty

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 234-8 Freescale Semiconductor Table 34-2 describes TCMODE fields

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 34-9 34.4.1.2 Cell Delineation State Ma

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 234-10 Freescale Semiconductor 34.4.1.3 TC Layer Event Register

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 34-11 34.4.1.4 TC Layer Mask Register (

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-1 Chapter 2 G2 CoreThe PowerQUICC II contains an embedded version of t

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 234-12 Freescale Semiconductor Table 34-6 describes TCGSR fields

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 34-13 34.4.3.6 Filtered Cell Counter [1

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 234-14 Freescale Semiconductor The TC layer requests ATM cells f

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 34-15 Figure 34-11. TC Operation in FCC

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 234-16 Freescale Semiconductor Figure 34-12. Example of Serial A

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 34-17 6. Program the Serial Interface (

ATM Transmission Convergence LayerMPC8260 PowerQUICC II Family Reference Manual, Rev. 234-18 Freescale Semiconductor Step 6Program the SI to retrieve

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-1 Chapter 35 Fast Ethernet ControllerThe Ethernet IEEE 802.3 protocol

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-2 Freescale Semiconductor 10-Mbps Ethernet basic timing specifications

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-3 • Performs framing functions— Preamble gener

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2x Freescale Semiconductor ContentsParagraphNumber TitlePageNumber7.2.4.4.2 Global (GBL)—Input ...

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-2 Freescale Semiconductor Figure 2-1. PowerQUICC II Integrated Processor Core Block Diag

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-4 Freescale Semiconductor — Busy (out of buffers)• Error counters— Dis

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-5 The PowerQUICC II has additional signals for

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-6 Freescale Semiconductor or for error situations. When the GRACEFUL S

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-7 35.6 Flow ControlBecause collisions cannot o

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-8 Freescale Semiconductor When an external CAM is used for address fil

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-9 0x68 TFCSTAT Hword Out-of-sequence TxBD. Inc

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-10 Freescale Semiconductor 0xB4 CF_RANGEHword Control frame range. Int

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-11 35.9 Programming ModelThe core configures a

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-12 Freescale Semiconductor NOTEBefore resetting the CPM, configure TX_

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-13 If an address from the hash table must be d

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-3 The processor core is a superscalar processor that can issue a

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-14 Freescale Semiconductor 35.12 Ethernet Address RecognitionThe Ether

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-15 CheckAddressI/G AddressIndividualAddr Match

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-16 Freescale Semiconductor Figure 35-4. Ethernet Address Recognition F

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-17 small fraction of frames from reaching memo

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-18 Freescale Semiconductor Transmission errors are described in Table

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-19 Table 35-8 describes FPSMR fields.012345678

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-20 Freescale Semiconductor 35.18.2 Ethernet Event Register (FCCE)/Mask

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-21 Table 35-9 describes FCCE/FCCM fields.Figur

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-22 Freescale Semiconductor Figure 35-7. Ethernet Interrupt Events Exam

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-23 Table 35-10 describes Ethernet RxBD fields.

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-4 Freescale Semiconductor — LSU for data transfer between data cache and GPRs and FPRs —

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-24 Freescale Semiconductor Data length is the number of octets the CP

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-25 Figure 35-9. Ethernet Receiving Using RxBDs

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-26 Freescale Semiconductor Table 35-11 describes Ethernet TxBD fields.

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 35-27 Data length is the number of octets the Eth

Fast Ethernet ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 235-28 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 36-1 Chapter 36 FCC HDLC ControllerLayer 2 of the seven-layer OSI model

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 236-2 Freescale Semiconductor • Four address comparison registers with masks• M

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 36-3 36.3 HDLC Channel Frame Reception ProcessingThe H

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 236-4 Freescale Semiconductor Figure 36-2 shows an example of using HMASK and H

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 36-5 Figure 36-2. HDLC Address Recognition Example36.5

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-5 Figure 2-1 shows how the execution units—IU, BPU, LSU, and SRU

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 236-6 Freescale Semiconductor Table 36-3 describes the receive commands that ap

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 36-7 36.6 HDLC Mode Register (FPSMR)When an FCC is con

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 236-8 Freescale Semiconductor The FPSMR fields are described in Table 36-6.0345

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 36-9 36.7 HDLC Receive Buffer Descriptor (RxBD)The HDL

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 236-10 Freescale Semiconductor Figure 36-4. FCC HDLC Receiving Using RxBDsBuffe

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 36-11 Figure 36-5 shows the FCC HDLC RxBD.Table 36-7 d

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 236-12 Freescale Semiconductor The RxBD status bits are written by the HDLC con

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 36-13 The TxBD status bits are written by the HDLC con

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 236-14 Freescale Semiconductor 36.9 HDLC Event Register (FCCE)/Mask Register (F

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 36-15 Figure 36-8 shows interrupts that can be generat

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-6 Freescale Semiconductor The BPU contains an adder to compute branch target addresses a

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 236-16 Freescale Semiconductor Figure 36-8. HDLC Interrupt Event Example36.10 F

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 36-17 Table 36-10 describes FCCS bits.Table 36-10. FC

FCC HDLC ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 236-18 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 37-1 Chapter 37 FCC Transparent ControllerThe FCC transparent controller

FCC Transparent ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 237-2 Freescale Semiconductor • Reverse data mode• Another protocol can

FCC Transparent ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 37-3 following the 8-bit SYNC. This effectively

FCC Transparent ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 237-4 Freescale Semiconductor Figure 37-2. Sending Transparent Frames be

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 38-1 Chapter 38 Serial Peripheral Interface (SPI)The serial peripheral i

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 238-2 Freescale Semiconductor • Works with data characters from 4

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 38-3 38.3 Configuring the SPI Controller

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-7 Load and store instructions are issued and translated in progr

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 238-4 Freescale Semiconductor When multiple TxBDs are ready, TxBD

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 38-5 Figure 38-3. Multimaster Configurat

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 238-6 Freescale Semiconductor mode. Gaps should be inserted betwe

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 38-7 Figure 38-5. SPI Transfer Format wi

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 238-8 Freescale Semiconductor Figure 38-6. SPI Transfer Format wi

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 38-9 with LEN=7 (data size=8), the follo

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 238-10 Freescale Semiconductor 38.4.3 SPI Command Register (SPCOM

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 38-11 Table 38-5. SPI Parameter RAM Memo

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 238-12 Freescale Semiconductor 38.5.1 Receive/Transmit Function C

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 38-13 38.7 The SPI Buffer Descriptor (BD

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-8 Freescale Semiconductor and data. The MMUs also control access privileges for these sp

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 238-14 Freescale Semiconductor — For a TxBD, this is the number o

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 38-15 38.7.1.2 SPI Transmit BD (TxBD)Dat

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 238-16 Freescale Semiconductor 38.8 SPI Master Programming Exampl

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 38-17 8. Initialize the TxBD. Assume the

Serial Peripheral Interface (SPI)MPC8260 PowerQUICC II Family Reference Manual, Rev. 238-18 Freescale Semiconductor NOTEIf the master sends 3 bytes an

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 39-1 Chapter 39 I2C ControllerThe inter-integrated circuit (I2C®) contro

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 239-2 Freescale Semiconductor 39.1 FeaturesThe following is a list of the I2C contro

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 39-3 because the R/W request follows the slave port address

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 239-4 Freescale Semiconductor A master write occurs as follows: 1. The master core s

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 39-5 3. After the first byte is shifted in, the slave compa

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-9 Note that there may be registers common to other processors th

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 239-6 Freescale Semiconductor 39.4 I2C RegistersThe following sections describe the

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 39-7 Table 39-2 describes I2ADD fields.39.4.3 I2C Baud Rate

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 239-8 Freescale Semiconductor Table 39-4 describes the I2CER/I2CMR fields.39.4.5 I2C

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 39-9 39.5 I2C Parameter RAMThe I2C controller parameter tab

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 239-10 Freescale Semiconductor Figure 39-11 shows the RFCR/TFCR bit fields.Table 39-

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 39-11 39.6 I2C CommandsThe I2C transmit and receive command

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 239-12 Freescale Semiconductor Figure 39-12. I2C Memory Structure39.7.1 I2C Buffer D

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 39-13 Table 39-9 describes I2C RxBD status and control bits

I2C ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 239-14 Freescale Semiconductor Table 39-10 describes I2C TxBD status and control bit

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 40-1 Chapter 40 Parallel I/O PortsThe CPM supports four general-purpose

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-10 Freescale Semiconductor Figure 2-2. PowerQUICC II Programming Model—RegistersDSISRSP

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 240-2 Freescale Semiconductor Table 40-1 describes PODR fields.40.2.2 Port Data

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 40-3 40.2.3 Port Data Direction Registers (PDIRA–PDIRD)

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 240-4 Freescale Semiconductor 40.2.4 Port Pin Assignment Register (PPAR)The port

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 40-5 PSOR bits are effective only if the corresponding

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 240-6 Freescale Semiconductor Figure 40-6. Port Functional Operation40.4 Port Pi

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 40-7 40.4.1 General Purpose I/O PinsEach one of the por

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 240-8 Freescale Semiconductor Figure 40-7. Primary and Secondary Option Programm

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 40-9 PA25FCC1: TxD[0]1 UTOPIA 8FCC1: TxD[8]1 UTOPIA 16M

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 240-10 Freescale Semiconductor PA17FCC1: RxD[7]1 UTOPIA 8FCC1: RxD[15]1UTOPIA 16

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 40-11 Table 40-6 shows the port B pin assignments.PA 9

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-11 2.3.1.2 PowerQUICC II-Specific RegistersThe set of registers

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 240-12 Freescale Semiconductor Table 40-6. Port B Dedicated Pin Assignment (PPA

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 40-13 PB19 FCC2: RxD[5]1 UTOPIA 8FCC2: RxD[2] MII/HDLC

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 240-14 Freescale Semiconductor Table 40-7 shows the port C pin assignments.PB6 F

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 40-15 PC25 FCC2: TxD[2]1 UTOPIA 8CLK7 GND BRG4: BRGO

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 240-16 Freescale Semiconductor PC10 FCC1: TxD[2]1UTOPIA 16 SCC3: CD SCC3: RENA E

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 40-17 Table 40-8 shows the port D pin assignments.1Not

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 240-18 Freescale Semiconductor PD21SCC4: TXD FCC1: RxD[3]1 UTOPIA 16GND TDM_A2:

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 40-19 40.6 Interrupts from Port CThe port C lines assoc

Parallel I/O PortsMPC8260 PowerQUICC II Family Reference Manual, Rev. 240-20 Freescale Semiconductor and/or CD to automatically control operation. Thi

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor A-1 Appendix ARegister Quick Reference GuideA0This section provides a bri

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xi ContentsParagraphNumber TitlePageNumber8.2.2 60x-Compatible Bus Mode..

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-12 Freescale Semiconductor 7 PAR Disable precharge of ARTRY.0 Precharge of ARTRY enabled

Register Quick Reference GuideMPC8260 PowerQUICC II Family Reference Manual, Rev. 2A-2 Freescale Semiconductor Table A-4 lists supervisor-level SPRs d

Register Quick Reference GuideMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor A-3 A.3 MPC8260-Specific SPRsTable A-2 and

Register Quick Reference GuideMPC8260 PowerQUICC II Family Reference Manual, Rev. 2A-4 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor B-1 Appendix BReference Manual (Rev 1) ErrataThis appendix lists errata t

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2B-2 Freescale Semiconductor 4.3.2.1, 4-28 The bit definitions shou

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor B-3 PCI controller can initiate global tra

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2B-4 Freescale Semiconductor 9.11.2.22, 9-62 In Figure 9-54, the re

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor B-5 #24 as shown). IDMA option 3 is shown

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2B-6 Freescale Semiconductor Also, replace the description of REV_N

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor B-7 must be negated no later than 15 ns af

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-13 18 ILOCK Instruction cache lock0 Normal operation 1 Instructi

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2B-8 Freescale Semiconductor occurs every 256 serial transmit clock

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor B-9 30.10.7, 30-84 In Table 30-41, change

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2B-10 Freescale Semiconductor 30.13.2, 30-92 In Table 30-47, replac

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor B-11 seven, TIRU event is reported, see Se

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2B-12 Freescale Semiconductor 33.4.1.1, 33-29 Add the following tw

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor B-13 33.4.7.1, 33- 47 Add DSL to Offset +

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2B-14 Freescale Semiconductor 33.5.4.5.1, 33-65 The order of steps

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor B-15 and transmitted a byte at a time with

Reference Manual (Rev 1) ErrataMPC8260 PowerQUICC II Family Reference Manual, Rev. 2B-16 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Glossary-1 Glossary of Terms and AbbreviationsThe glossary contains an al

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-14 Freescale Semiconductor 2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Glossary-2 Freescale Semiconductor Although the architecture does not prescribe the exact behavio

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Glossary-3 Critical-data first. An aspect of burst accesses that allow th

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Glossary-4 Freescale Semiconductor F Fetch. Retrieving instructions from either the cache or main

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Glossary-5 Interrupt. An asynchronous exception. On PowerPC processors, i

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Glossary-6 Freescale Semiconductor Munging. A modification performed on an effective address that

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Glossary-7 Physical memory. The actual memory that can be accessed throug

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Glossary-8 Freescale Semiconductor Reservation. The processor establishes a reservation on a cach

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Glossary-9 Supervisor mode. The privileged operation state of a processor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Glossary-10 Freescale Semiconductor Write-back. A cache memory update policy in which processor w

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-1 IndexNumerics603efeatures list, 2-360x bus60x-compatible mode60x-

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-15 2.3.1.2.4 Processor Version Register (PVR)Software can identi

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-2 Freescale Semiconductor A–A Indexinternal statistics tables, 31-43interworking functionsa

Index B–BMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-3 interrupt queues, 30-81maximum performance configuratio

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-4 Freescale Semiconductor C–C IndexBISYNC mode, 23-12definition, 31-22fast communications c

Index C–CMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-5 ATM controllerAAL1 sequence number protection table, 30

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-6 Freescale Semiconductor C–C Indexblock diagram, 16-2overview, 16-1dual-port RAMaccessing

Index C–CMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-7 buffer chaining, 19-16buffers, 19-24bus exceptions, 19-

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-8 Freescale Semiconductor D–D Indexmaster mode, 38-3maximum receive buffer length (MRBLR),

Index E–FMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-9 block diagram, 14-18buffer descriptors, 14-20memory map

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-10 Freescale Semiconductor G–H Indexsaving power, 29-22switching protocols, 29-22timing con

Index I–IMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-11 accessing the bus, 22-18bus controller, 22-16collision

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-16 Freescale Semiconductor 2.3.2.2 PowerPC Instruction SetThe PowerPC instructions are d

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-12 Freescale Semiconductor I–I IndexIDMR (IDMA mask registers), 19-24IDSR (IDMA event (stat

Index J–MMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-13 IDCR mode group activation, 33-74start-up, 33-73link a

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-14 Freescale Semiconductor M–M Indexinterface signals, 11-52MPC8xx versus MPC8260, 11-63OE

Index N–PMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-15 address latch enable (ALE), 11-10data streaming mode,

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-16 Freescale Semiconductor P–P Indexoverview, 20-13UART mode, 21-3serial management control

Index P–PMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-17 inbound door bell machine check, 9-100inbound post que

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-18 Freescale Semiconductor R–R IndexHDLC bus protocol, 22-22PSMR (protocol-specific mode re

Index R–RMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-19 I2COM, 39-8I2MOD, 39-6IDMA emulationDCM, 19-19IDMR, 19

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-20 Freescale Semiconductor R–R IndexI2O unitI2O registersinbound FIFO queue port register (

Index R–RMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-21 serial management controllers(SMCs)GCI modeTxBD, 27-34

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-17 Integer instructions operate on byte, half-word, and word ope

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-22 Freescale Semiconductor S–S IndexRSR (reset status) register, 5-4RSTATE (internal receiv

Index S–SMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-23 controlling SCC timing, 20-17DPLL operation, 20-21feat

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-24 Freescale Semiconductor S–S IndexTxBD, 27-27UART modecharacter mode, 27-11commands, 27-1

Index T–TMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-25 BCR, 4-26block diagram, 4-1bus monitor, 4-3clocks, 4-3

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-26 Freescale Semiconductor U–U IndexTESCRx (60x bus error status and control registers), 4-

Index U–UMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor Index-27 data sample control, 11-77data valid, 11-77differences

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Index-28 Freescale Semiconductor U–U Index

Part I—Overview IOverview 1G2 Core 2Memory Map 3Part II—Configuration and Reset IISystem Interface Unit (SIU) 4Reset 5Part III—The Hardware Interface

I Part I—Overview1 Overview2 G2 Core3 Memory MapII Part II—Configuration and Reset4 System Interface Unit (SIU)5 ResetIII Part III—The Hardware Inter

Fast Ethernet Controller 35FCC HDLC Controller 36FCC Transparent Controller 37Serial Peripheral Interface (SPI) 38I2C Controller 39Parallel I/O Ports

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-18 Freescale Semiconductor 2.4.1 PowerPC Cache ModelThe PowerPC architecture does not de

35 Fast Ethernet Controller36 FCC HDLC Controller37 FCC Transparent Controller38 Serial Peripheral Interface (SPI)39 I2C Controller40 Parallel I/O Po

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-19 Figure 2-6. Data Cache OrganizationBecause the processor core

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-20 Freescale Semiconductor tenures of a read operation). Because the processor can dynam

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-21 2.5 Exception ModelThis section describes the PowerPC excepti

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xii Freescale Semiconductor ContentsParagraphNumber TitlePageNumber9.6 60x Bus Arbitration Priori

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-22 Freescale Semiconductor exception is taken due to a trap or system call instruction,

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-23 Machine check 00200 A machine check is caused by the assertio

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-24 Freescale Semiconductor Program 00700 A program exception is caused by one of the fol

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-25 2.5.3 Exception PrioritiesThe exception priorities for the pr

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-26 Freescale Semiconductor TLB with memory. In the PowerQUICC II, the processor core’s T

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 2-27 2.7 Instruction TimingThe processor core is a pipelined super

G2 CoreMPC8260 PowerQUICC II Family Reference Manual, Rev. 22-28 Freescale Semiconductor 2.8 Differences between the PowerQUICC II’s G2 Core and the M

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-1 Chapter 3 Memory MapThe PowerQUICC II’s internal memory resources ar

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-2 Freescale Semiconductor 0x10029 Reserved — 24 bits — —0x1002C 60x bus arbitration-l

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-3 0x1012C Option register bank 5 (OR5) R/W 32 bits undefined

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xiii ContentsParagraphNumber TitlePageNumber9.11.1.5 PCI Outbound Compari

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-4 Freescale Semiconductor 0x101A5 Reserved — 24 bits — —0x101A8 Internal memory map r

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-5 0x10458 Outbound message register 0 (OMR0)2R/W 32 bits unde

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-6 Freescale Semiconductor 0x10608 DMA 2 current descriptor address register (DMACDAR2

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-7 0x108E0 PCI inbound comparison mask register 1 (PICMR1)2R/W

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-8 Freescale Semiconductor 0x10D0C Port A open drain register (PODRA) R/W 32 bits 0x00

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-9 0x10D98 Timer 1 capture register (TCR1) R/W 16 bits 0x0000

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-10 Freescale Semiconductor 0x11030 IDMA 3 event register (IDSR3) R/W 8 bits 0x00 19.8

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-11 0x11319 Reserved — 24 bits — —0x1131C FCC1 transmit inter

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-12 Freescale Semiconductor 0x1133C FCC2 transmit internal rate registers for PHY0 (F

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-13 TC Layer 140x11400 TC1 mode register (TCMODE1)4R/W 16 bits

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xiv Freescale Semiconductor ContentsParagraphNumber TitlePageNumber9.11.2.27 PCI Configuration Re

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-14 Freescale Semiconductor 0x1144C TC3 corrected cells counter (TC_CCC3)4R/W 16 bits

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-15 0x114A2 TC6 cell delineation state machine register (CDSMR

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-16 Freescale Semiconductor 0x114F2 TC8 error cells counter (TC_ECC8)4R/W 16 bits 0x00

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-17 0x119D6 CP timers event register (RTER) R/W 16 bits 0x0000

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-18 Freescale Semiconductor 0x11A17 SCC1 status register (SCCS1) R/W 8 bits 0x00 21.20

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-19 0x11A37 SCC2 status register (SCCS2) R/W 8 bits 0x00 21.20

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-20 Freescale Semiconductor 0x11A57 SCC3 status register (SCCS3) R/W 8 bits 0x00 21.20

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-21 0x11A78–0x11A7FReserved — 8 bytes — —SMC10x11A82 SMC1 mod

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-22 Freescale Semiconductor 0x11B03 Reserved — 8 bits — —0x11B04 CPM mux FCC clock rou

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 3-23 SI2 Registers0x11B40 SI2 TDMA2 mode register (SI2AMR) R/W

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xv ContentsParagraphNumber TitlePageNumber9.13.1.6.2 DMA Status Register

Memory MapMPC8260 PowerQUICC II Family Reference Manual, Rev. 23-24 Freescale Semiconductor 0x12C00–0x12DFF SI 2 receive routing RAM (SI2RxRAM) R/W 51

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor II-1 Part IIConfiguration and ResetIntended AudiencePart II is intended f

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2II-2 Freescale Semiconductor example, MSR[LE] refers to the little-endian mode enable bit in the

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-1 Chapter 4 System Interface Unit (SIU)The system interface unit (SIU)

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-2 Freescale Semiconductor generates the clock signals used by the SI

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-3 Figure 4-2 is a block diagram of the syste

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-4 Freescale Semiconductor Figure 4-3. Timers Clock GenerationFor det

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-5 Figure 4-4. TMCNT Block DiagramSection 4.3

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-6 Freescale Semiconductor This gives a range from 122 µs (PITC = 0x0

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-7 Figure 4-7. Software Watchdog Timer Block

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xvi Freescale Semiconductor ContentsParagraphNumber TitlePageNumber10.6 PowerQUICC II Internal Cl

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-8 Freescale Semiconductor 4.2.1 Interrupt ConfigurationFigure 4-8 sh

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-9 If the software watchdog timer is programm

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-10 Freescale Semiconductor relative ordering of the interrupts, but,

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-11 27 YCC8 (Grouped) Yes28 XSIU4 (Spread) No

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-12 Freescale Semiconductor Notice the lack of SDMA interrupt sources

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-13 • Spread. In the spread scheme, prioritie

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-14 Freescale Semiconductor Figure 4-9. Interrupt Request Masking4.2.

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-15 6 IDMA1 0b00_01107 IDMA2 0b00_01118 IDMA3

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-16 Freescale Semiconductor Note that the interrupt vector table diff

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-17 Requests can be masked independently in t

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xvii ContentsParagraphNumber TitlePageNumber11.4 SDRAM Machine ...

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-18 Freescale Semiconductor The SICR register bits are described in T

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-19 4.3.1.3 CPM Interrupt Priority Registers

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-20 Freescale Semiconductor The CPM low interrupt priority register (

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-21 4.3.1.4 SIU Interrupt Pending Registers (

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-22 Freescale Semiconductor When a pending interrupt is handled, the

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-23 Figure 4-17 shows SIMR_L.Note the followi

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-24 Freescale Semiconductor 4.3.1.6 SIU Interrupt Vector Register (SI

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-25 Figure 4-19. Interrupt Table Handling Exa

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-26 Freescale Semiconductor Table 4-8 describes SIEXR fields.4.3.2 Sy

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-27 Figure 4-9 describes BCR fields.0 1 3 4 5

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described product contains a PowerPC processor core. The PowerP

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xviii Freescale Semiconductor ContentsParagraphNumber TitlePageNumber11.6.1.4 Exception Requests.

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-28 Freescale Semiconductor 11 EAV Enable address visibility. Normall

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-29 4.3.2.2 60x Bus Arbiter Configuration Reg

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-30 Freescale Semiconductor 4.3.2.3 60x Bus Arbitration-Level Registe

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-31 PPC_ALRL, shown in Figure 4-24, defines a

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-32 Freescale Semiconductor 4.3.2.5 Local Bus Arbitration Level Regis

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-33 4.3.2.6 SIU Module Configuration Register

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-34 Freescale Semiconductor 2 PBSE Parity byte select enable. 0 Parit

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-35 10–11 APPC Address parity pins configurat

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-36 Freescale Semiconductor 4.3.2.7 Internal Memory Map Register (IMM

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-37 4.3.2.8 System Protection Control Registe

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xix ContentsParagraphNumber TitlePageNumberChapter 13 IEEE 1149.1 Test A

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-38 Freescale Semiconductor Table 4-14 describes SYPCR fields.4.3.2.9

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-39 Table 4-15 describes TESCR1 fields. 0123

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-40 Freescale Semiconductor 4.3.2.11 60x Bus Transfer Error Status an

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-41 The TESCR2 register is described in Table

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-42 Freescale Semiconductor 4.3.2.12 Local Bus Transfer Error Status

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-43 4.3.2.13 Local Bus Transfer Error Status

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-44 Freescale Semiconductor 4.3.2.14 Time Counter Status and Control

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-45 4.3.2.16 Time Counter Alarm Register (TMC

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-46 Freescale Semiconductor 4.3.3 Periodic Interrupt RegistersThe per

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-47 Table 4-22 describes PITC fields.4.3.3.3

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xx Freescale Semiconductor ContentsParagraphNumber TitlePageNumber14.6.7 RISC Timer Initializatio

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-48 Freescale Semiconductor Table 4-23 describes PITR fields. 4.3.4 P

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 4-49 Table 4-24 describes PCIBRx fields.4.3.4.

System Interface Unit (SIU)MPC8260 PowerQUICC II Family Reference Manual, Rev. 24-50 Freescale Semiconductor Table 4-26. SIU Pins Multiplexing Control

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 5-1 Chapter 5 ResetThe PowerQUICC II has several inputs to the reset log

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 25-2 Freescale Semiconductor 5.1.1 Reset ActionsThe reset block has a reset control logic tha

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 5-3 Figure 5-4 shows the power-on reset flow.Figure 5-1. Power-on Re

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 25-4 Freescale Semiconductor 5.2 Reset Status Register (RSR)The reset status register (RSR),

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 5-5 NOTEThe Reset Status Register accumulates reset events. For exam

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 25-6 Freescale Semiconductor 5.4 Reset ConfigurationVarious features may be configured during

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 5-7 The configuration words for all PowerQUICC IIs are assumed to re

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xxi ContentsParagraphNumber TitlePageNumber16.4.3 CMX SI2 Clock Route Reg

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 25-8 Freescale Semiconductor 5.4.1 Hard Reset Configuration WordThe contents of the hard rese

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 5-9 13–15 ISB Initial internal space base select. Defines the initia

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 25-10 Freescale Semiconductor 5.4.2 Hard Reset Configuration ExamplesThis section presents so

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 5-11 Figure 5-6. Configuring a Single Chip from EPROM5.4.2.3 Multipl

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 25-12 Freescale Semiconductor Figure 5-7. Configuring Multiple ChipsIn this system, the confi

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 5-13 shows, this complex configuration is done without additional gl

ResetMPC8260 PowerQUICC II Family Reference Manual, Rev. 25-14 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor III-1 Part IIIThe Hardware InterfaceIntended AudiencePart III is intended

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2III-2 Freescale Semiconductor MPC82xx DocumentationSupporting documentation for the PowerQUICC II

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor III-3 CPM Communications processor moduleCRC Cyclic redundancy check DMA

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xxii Freescale Semiconductor ContentsParagraphNumber TitlePageNumber19.5.2 Memory to/from Periphe

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2III-4 Freescale Semiconductor PRI Primary rate interfaceRx ReceiveSCC Serial communications contr

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 6-1 Chapter 6 External SignalsThis chapter describes the external signal

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 26-2 Freescale Semiconductor Figure 6-1. PowerQUICC II External Signals6.2 Signal

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 6-3 Table 6-1. External Signals Signal DescriptionBR60x

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 26-4 Freescale Semiconductor DBBIRQ360x data bus busy—(Input/output) As an output

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 6-5 IRQ3DP[3]CKSTP_OUTEXT_BR3Interrupt request 3—This inp

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 26-6 Freescale Semiconductor IRQ7DP[7]CSE[1]Interrupt request 7—This input is one

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 6-7 WTBADDR30IRQ3Write through—Output used for L2 cache c

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 26-8 Freescale Semiconductor CS[11]AP[0]Chip select—Output that enable specific me

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 6-9 PSDCASPGPL360x bus SDRAM CAS—Output from the 60x bus

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xxiii ContentsParagraphNumber TitlePageNumber20.1.3 Data Synchronization

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 26-10 Freescale Semiconductor LSDWELGPL1PCI_MODCK_H11Local bus SDRAM write enable—

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 6-11 L_A15SMIPCI_FRAME1Local bus address 15—Local bus add

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 26-12 Freescale Semiconductor L_A22PCI_SERR1Local bus address 22—Local bus address

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 6-13 L_A27PCI_GNT21CPCI_HS_ENUM1Local bus address 27—Loca

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 26-14 Freescale Semiconductor LCL_DP[0–3]PCI_C/BE[3-0]1Local bus data parity—Local

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 6-15 RSTCONFRSTCONF —Input used during reset configuratio

External SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 26-16 Freescale Semiconductor PA[0–31] General-purpose I/O port A bits 0–31—CPM po

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 7-1 Chapter 7 60x SignalsThis chapter describes the PowerQUICC II proces

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 27-2 Freescale Semiconductor 7.1 Signal ConfigurationFigure shows the grouping of the

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 7-3 7.2.1 Address Bus Arbitration SignalsThe address arbitrati

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xxiv Freescale Semiconductor ContentsParagraphNumber TitlePageNumber21.18 SCC UART Transmit Buffe

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 27-4 Freescale Semiconductor a snoop copyback; may also be negated if the external mast

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 7-5 7.2.1.3 Address Bus Busy (ABB)The address bus busy (ABB) s

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 27-6 Freescale Semiconductor bus request if the transfer attributes TT[0–4] indicate th

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 7-7 State Meaning Asserted—Indicates that another device has b

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 27-8 Freescale Semiconductor High Impedance—Same as A[0–31].7.2.4.3 Transfer Burst (TBS

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 7-9 State Meaning Asserted—Indicates that the transaction in p

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 27-10 Freescale Semiconductor State Meaning Asserted—Indicates that a 60x bus slave is

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 7-11 Timing Comments Assertion—May occur as early as the secon

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 27-12 Freescale Semiconductor Negated—Indicates that an external device is not granted

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 7-13 State Meaning The data bus holds 8 byte lanes assigned as

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xxv ContentsParagraphNumber TitlePageNumber23.5 SCC BISYNC Commands ...

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 27-14 Freescale Semiconductor State Meaning Asserted/Negated—Represents odd parity for

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 7-15 asserted for each data beat in a burst transaction. For m

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 27-16 Freescale Semiconductor Negation—Occurs after the clock cycle of the final (or on

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 7-17 transaction,. For more information, see Section 8.5.5, “P

60x SignalsMPC8260 PowerQUICC II Family Reference Manual, Rev. 27-18 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-1 Chapter 8 The 60x BusThe 60x bus, which is used by processors that i

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-2 Freescale Semiconductor 8.2 Bus ConfigurationThe 60x bus supports separate bus con

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-3 Figure 8-1. Single-PowerQUICC II Bus Mode NOTEIn single-Po

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-4 Freescale Semiconductor operations and maintains coherency between the primary cac

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-5 require data transfer termination signals for each beat of

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xxvi Freescale Semiconductor ContentsParagraphNumber TitlePageNumberChapter 25 SCC Ethernet Mode

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-6 Freescale Semiconductor system reset by sampling configuration pins. See Section 4

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-7 External arbitration (as provided by the PowerQUICC II) is

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-8 Freescale Semiconductor with BG INT-asserted (note that BG INT is an internal sign

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-9 Figure 8-5. Address Pipelining 8.4.3 Address Transfer Attr

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-10 Freescale Semiconductor Table 8-2. Trans fer Type Encoding TT[0–4]160x Bus Specif

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-11 NOTERegarding Table 8-2:1XX01 Reserved for customer— Not

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-12 Freescale Semiconductor • For reads, the processor cleans or flushes during a sno

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-13 The PowerQUICC II supports critical-word-first burst tran

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-14 Freescale Semiconductor Each data beat is terminated with an assertion of TA.8.4.

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-15 The PowerQUICC II supports misaligned memory operations,

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xxvii ContentsParagraphNumber TitlePageNumberChapter 27 Serial Managemen

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-16 Freescale Semiconductor 8.4.3.6 Effect of Port Size on Data TransfersThe PowerQUI

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-17 Figure 8-6. Interface to Different Port Size Devices031 6

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-18 Freescale Semiconductor 8.4.3.7 60x-Compatible Bus Mode—Size CalculationTo comply

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-19 calculation state machine. Note that the address and size

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-20 Freescale Semiconductor 16-, or 24-byte extended transfers. These transactions ar

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-21 Table 8-12. Address and Size State for Extended Transfers

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-22 Freescale Semiconductor Extended transfer mode is enabled by setting the BCR[ETM]

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-23 Figure 8-7. Retry CycleAs a bus master, the PowerQUICC II

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-24 Freescale Semiconductor TA/ARTRY relationship is not met, the master may enter an

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-25 one-level pipelining). When the internal arbiter counts a

Part I—Overview IOverview 1G2 Core 2Memory Map 3Part II—Configuration and Reset IISystem Interface Unit (SIU) 4Reset 5Part III—The Hardware Interface

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xxviii Freescale Semiconductor ContentsParagraphNumber TitlePageNumber27.4.11 SMC Transparent NMS

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-26 Freescale Semiconductor • External masters connected to the 60x bus must assert D

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-27 Figure 8-8 shows both a single-beat and burst data transf

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-28 Freescale Semiconductor Figure 8-9. 28-Bit Extended Transfer to 32-Bit Port SizeF

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-29 Figure 8-10. Burst Transfer to 32-Bit Port Size8.5.6 Data

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-30 Freescale Semiconductor Figure 8-11. Data Tenure Terminated by Assertion of TEATh

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 8-31 snooping condition). No snoop update to the PowerQUICC II

The 60x BusMPC8260 PowerQUICC II Family Reference Manual, Rev. 28-32 Freescale Semiconductor 8.7.1 Support for the lwarx/stwcx. Instruction PairThe lo

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-1 Chapter 9 PCI BridgeNOTEThe functionality described in this chapter

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-2 Freescale Semiconductor Figure 9-1. PCI Bridge in the PowerQUICC IIFigure 9-2. PCI

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-3 9.1 SignalsTo avoid the need for additional pins, the PCI b

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xxix ContentsParagraphNumber TitlePageNumber28.3.4.3 SS7 Configuration Re

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-4 Freescale Semiconductor NOTEAlthough the user can direct the SDMA to the 60x bus, t

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-5 9.8 CompactPCI Hot Swap Specification SupportCompactPCI is

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-6 Freescale Semiconductor • Address translation units for address mapping between hos

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-7 9.9.1.2 PCI Protocol FundamentalsThe bus transfer mechanism

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-8 Freescale Semiconductor 9.9.1.2.1 Basic Transfer ControlPCI data transfers are cont

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-9 line, and disconnects after reading one cache line. If AD[1

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-10 Freescale Semiconductor A read transaction starts when FRAME is asserted for the f

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-11 Figure 9-5. Single Beat Write ExampleFigure 9-6 shows an e

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-12 Freescale Semiconductor When the PCI bridge as a target needs to suspend a transac

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-13 • AD[1-0] is 0bx1 (a reserved burst ordering encoding) dur

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xxx Freescale Semiconductor ContentsParagraphNumber TitlePageNumberChapter 29 Fast Communication

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-14 Freescale Semiconductor target qualifies the address/data lines with FRAME before

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-15 For core- or DMA-initiated transfers, the PCI bridge strea

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-16 Freescale Semiconductor the AD lines, reaches a stable value. This means that a va

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-17 When the CONFIG_ADDRESS register gets written with a value

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-18 Freescale Semiconductor 9.9.1.5.2 Error ReportingExcept for setting the detected-p

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-19 As a target that asserts SERR on an address parity, the PC

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-20 Freescale Semiconductor is the master that is currently using the bus, and the hig

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-21 completes one more data phase and relinquishes the bus. Th

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-22 Freescale Semiconductor • If the transaction address is within one of the two inbo

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-23 NOTEWhen a transaction is performed by a PCI master, the b

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xxxi ContentsParagraphNumber TitlePageNumber30.2.1.4 AAL2 Transmitter Ove

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-24 Freescale Semiconductor Figure 9-14. Address Map Example9.10.1 Address Map Program

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-25 are routed to the PCI bus with address translation disable

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-26 Freescale Semiconductor 9.10.2.2 PCI Outbound TranslationOutbound address translat

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-27 9.11 Configuration RegistersThere are two types of configu

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-28 Freescale Semiconductor 0x10458 Outbound message register 0 (OMR0) R/W undefined 9

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-29 0x10608 DMA 2 current descriptor address register (DMACDAR

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-30 Freescale Semiconductor 9.11.1.1 Message Unit (I2O) RegistersMessage unit register

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-31 9.11.1.4 PCI Outbound Base Address Registers (POBARx) The

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-32 Freescale Semiconductor Figure 9-19. PCI Outbound Comparison Mask Registers (POCMR

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-33 Figure 9-20. Discard Timer Control register (PTCR)Table 9-

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xxxii Freescale Semiconductor ContentsParagraphNumber TitlePageNumber30.6.1 ATM-Layer OAM Definit

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-34 Freescale Semiconductor Figure 9-21. General Purpose Control Register (GPCR)Table

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-35 9.11.1.8 PCI General Control Register (PCI_GCR) The PCI ge

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-36 Freescale Semiconductor Figure 9-23. Error Status Register (ESR)Table 9-10. descri

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-37 9.11.1.10 Error Mask Register (EMR) The error mask registe

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-38 Freescale Semiconductor 9.11.1.11 Error Control Register (ECR) The error control r

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-39 9.11.1.12 PCI Error Address Capture Register (PCI_EACR) Th

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-40 Freescale Semiconductor 9.11.1.13 PCI Error Data Capture Register (PCI_EDCR) The P

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-41 Figure 9-28. PCI Error Control Capture Register (PCI_ECCR)

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-42 Freescale Semiconductor 9.11.1.15 PCI Inbound Translation Address Registers (PITAR

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-43 in a PIBARx register causes a change in the GPLABARx in th

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xxxiii ContentsParagraphNumber TitlePageNumber30.10.2.3.5 AAL2 Protocol-S

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-44 Freescale Semiconductor Figure 9-31. PCI Inbound Comparison Mask Registers (PICMRx

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-45 9.11.2 PCI Bridge Configuration Registers The PCI Local B

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-46 Freescale Semiconductor Figure 9-32. PCI Bridge PCI Configuration RegistersThe PCI

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-47 Figure 9-33. Vendor ID Register9.11.2.2 Device ID Register

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-48 Freescale Semiconductor 9.11.2.4 PCI Bus Status Register The PCI bus status regist

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-49 Figure 9-36. PCI Bus Status RegisterTable 9-23. describes

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-50 Freescale Semiconductor Figure 9-37. Revision ID Register9.11.2.6 PCI Bus Programm

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-51 Figure 9-39. Subclass Code Register9.11.2.8 PCI Bus Base C

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-52 Freescale Semiconductor Figure 9-41. PCI Bus Cache Line Size Register9.11.2.10 PCI

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-53 Figure 9-43. Header Type Register9.11.2.12 BIST Control Re

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xxxiv Freescale Semiconductor ContentsParagraphNumber TitlePageNumber30.12.2.3 UTOPIA Loop-Back M

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-54 Freescale Semiconductor Figure 9-45. PCI Bus Internal Memory-Mapped Registers Base

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-55 Figure 9-46. General Purpose Local Access Base Address Reg

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-56 Freescale Semiconductor 9.11.2.16 Subsystem Device ID Register Figure 9-48 and Tab

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-57 Figure 9-50. PCI Bus Interrupt Line Register 9.11.2.19 PCI

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-58 Freescale Semiconductor 9.11.2.21 PCI Bus MAX LAT Figure 9-53 and Table 9-40 descr

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-59 9.11.2.23 PCI Bus Arbiter Configuration Register The PCI b

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-60 Freescale Semiconductor Table 9-42. describes the PCI bus arbiter configuration re

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-61 9.11.2.25 PCI Hot Swap Control Status Register Figure 9-5

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-62 Freescale Semiconductor 9.11.2.26 PCI Configuration Register Access from the Core

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-63 9.11.2.27.1 Additional Information on Endianess The endian

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xxxv ContentsParagraphNumber TitlePageNumber31.8 AAL-1 Memory Structure..

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-64 Freescale Semiconductor Therefore, to set CTM in PCI DMA0 mode register, 0x0000000

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-65 • Accesses to PCI configuration registers are indirect (th

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-66 Freescale Semiconductor turn causes an interrupt to the local processor that imple

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-67 Figure 9-61. Outbound Message Registers (OMRx)9.12.2 Door

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-68 Freescale Semiconductor Figure 9-62. Outbound Doorbell Register (ODR)9.12.2.2 Inbo

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-69 9.12.3 I2O Unit The Intelligent Input Output specification

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-70 Freescale Semiconductor Figure 9-64. I2O Message QueueI2O defines extensions for t

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-71 The following registers should be accessed only from the 6

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-72 Freescale Semiconductor Figure 9-66. Inbound Free_FIFO Tail Pointer Register (IFTP

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-73 Figure 9-67. Inbound Post_FIFO Head Pointer Register (IPHP

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xxxvi Freescale Semiconductor ContentsParagraphNumber TitlePageNumber32.4.1 Receiver Overview ...

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-74 Freescale Semiconductor 9.12.3.3 Outbound FIFOs The outbound queues are used to se

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-75 Free MFAs are picked up by the local processor pointed to

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-76 Freescale Semiconductor An external PCI master reads the outbound queue port regis

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-77 Figure 9-72. Outbound Post_FIFO Tail Pointer Register (OPT

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-78 Freescale Semiconductor 9.12.3.4.2 Outbound FIFO Queue Port Register (OFQPR) OFQP

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-79 Figure 9-75. Outbound Message Interrupt Status Register (O

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-80 Freescale Semiconductor Figure 9-76. Outbound Message Interrupt Mask Register (OMI

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-81 Figure 9-77. Inbound Message Interrupt Status Register (IM

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-82 Freescale Semiconductor 9.12.3.4.6 Inbound Message Interrupt Mask Register (IMIMR)

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-83 9.12.3.4.7 Messaging Unit Control Register (MUCR) This reg

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xxxvii ContentsParagraphNumber TitlePageNumber33.3.2.4 Differences in CTC

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-84 Freescale Semiconductor 9.12.3.4.8 Queue Base Address Register (QBAR) This registe

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-85 9.13 DMA ControllerThe PCI bridge’s DMA controller transfe

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-86 Freescale Semiconductor address. The DMA controller assumes that the source and de

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-87 • First clear then set the CS (channel start) bit in the m

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-88 Freescale Semiconductor 60x bus, or when no data is left to transfer. Reading from

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-89 Table 9-66. DMAMRx Field DescriptionsBits Name Description

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-90 Freescale Semiconductor 9.13.1.6.2 DMA Status Register [0–3] (DMASRx) The status r

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-91 9.13.1.6.3 DMA Current Descriptor Address Register [0–3] (

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-92 Freescale Semiconductor 9.13.1.6.4 DMA Source Address Register [0–3] (DMASARx) The

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-93 The choice between PCI or 60x is done according to the fol

I Part I—Overview1 Overview2 G2 Core3 Memory MapII Part II—Configuration and Reset4 System Interface Unit (SIU)5 ResetIII Part III—The Hardware Inter

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xxxviii Freescale Semiconductor ContentsParagraphNumber TitlePageNumber33.4.6.2 Delay Compensatio

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-94 Freescale Semiconductor 9.13.1.6.7 DMA Next Descriptor Address Register [0–3] (DMA

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-95 9.13.2 DMA Segment DescriptorsDMA segment descriptors cont

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-96 Freescale Semiconductor Figure 9-89. DMA Chain of Segment Descriptors9.13.2.1 Desc

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-97 Byte Count = 0x67452301 <MSB..LSB>9.13.2.2 Descripto

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-98 Freescale Semiconductor 9.14.1.1.1 System Error (SERR)The SERR signal is used to r

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 9-99 9.14.1.3.1 Address Parity ErrorIf the PCI bridge is acting

PCI BridgeMPC8260 PowerQUICC II Family Reference Manual, Rev. 29-100 Freescale Semiconductor 9.14.1.3.4 Target-Abort ErrorIf a PCI transaction initiat

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 10-1 Chapter 10 Clocks and Power ControlThe PowerQUICC II’s clocking arc

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 210-2 Freescale Semiconductor 10.4 Main PLLThe main PLL performs frequency

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 10-3 output frequency is twice the CPM frequency.

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xxxix ContentsParagraphNumber TitlePageNumber33.5.4.3.2 As Responder (RX)

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 210-4 Freescale Semiconductor Figure 10-2. PCI Bridge as an Agent, Operati

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 10-5 NOTEIf a clock buffer is used in the feedbac

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 210-6 Freescale Semiconductor 10.7 PLL Pins Table 10-1 shows dedicated PLL

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 10-7 Figure 10-4 shows the filtering circuit for

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 210-8 Freescale Semiconductor 10.8 System Clock Control Register (SCCR)The

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 10-9 10.9 System Clock Mode Register (SCMR)The sy

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 210-10 Freescale Semiconductor The relationships among these parameters ar

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 10-11 10.10 Basic Power StructureThe I/O buffers,

Clocks and Power ControlMPC8260 PowerQUICC II Family Reference Manual, Rev. 210-12 Freescale Semiconductor The PowerQUICC II supports the two followin

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-1 Chapter 11 Memory ControllerThe memory controller is responsible fo

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xl Freescale Semiconductor ContentsParagraphNumber TitlePageNumber34.4.2.1 TC Layer General Event

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-2 Freescale Semiconductor • 18-bit address and 32-bit local data bus memory c

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-3 11.1 FeaturesThe memory controller’s main features

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-4 Freescale Semiconductor — User-specified control-signal patterns run when a

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-5 Figure 11-2. Memory Controller Machine SelectionSom

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-6 Freescale Semiconductor Figure 11-3. Simple System ConfigurationImplementat

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-7 Figure 11-4. Basic Memory Controller OperationThe S

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-8 Freescale Semiconductor register each time a bus-cycle access is requested.

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-9 • An ECC double-bit error• An ECC single bit error

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-10 Freescale Semiconductor Note that this feature cannot be used with L2 cach

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-11 11.2.13 Partial Data Valid Indication (PSDVAL)The

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xli ContentsParagraphNumber TitlePageNumber35.15 Handling Collisions ...

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-12 Freescale Semiconductor 11.2.14 BADDR[27:31] Signal ConnectionsThe memory

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-13 11.3.1 Base Registers (BRx)The base registers (BR0

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-14 Freescale Semiconductor 23 WP Write protect. Can restrict write accesses w

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-15 11.3.2 Option Registers (ORx)The ORx registers def

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-16 Freescale Semiconductor Table 11-5. ORx Field Descriptions (SDRAM Mode)Bit

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-17 Figure 11-8 shows ORx as it is formatted for GPCM

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-18 Freescale Semiconductor 19 BCTLD Data buffer control disable. Disables the

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-19 NOTEGPCM produces a glitch on the BSx lines when t

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-20 Freescale Semiconductor 11.3.3 60x SDRAM Mode Register (PSDMR)The 60x SDRA

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-21 Table 11-8. PSDMR Field DescriptionsBits Name Desc

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xlii Freescale Semiconductor ContentsParagraphNumber TitlePageNumber38.3.1 The SPI as a Master De

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-22 Freescale Semiconductor SDRAM Device–Specific Parameters:14–16 RFRC Refres

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-23 11.3.4 Local Bus SDRAM Mode Register (LSDMR)The LS

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-24 Freescale Semiconductor 2–4 OP SDRAM operation. Selects the operation that

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-25 SDRAM Device–Specific Parameters:14–16 RFRC Refres

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-26 Freescale Semiconductor 11.3.5 Machine A/B/C Mode Registers (MxMR)The mach

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-27 Table 11-10. Machine x Mode Registers (MxMR)Bits N

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-28 Freescale Semiconductor 11.3.6 Memory Data Register (MDR)The memory data r

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-29 Table 11-11 describes MDR fields.11.3.7 Memory Add

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-30 Freescale Semiconductor 11.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)Th

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-31 11.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xliii ContentsParagraphNumber TitlePageNumberChapter 40 Parallel I/O Por

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-32 Freescale Semiconductor Table 11-16 describes LSRT fields. 11.3.12 Memory

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-33 11.3.13 60x Bus Error Status and Control Registers

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-34 Freescale Semiconductor yFigure 11-19. 128-Mbyte SDRAM (Eight-Bank Configu

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-35 11.4.1 Supported SDRAM ConfigurationsThe PowerQUIC

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-36 Freescale Semiconductor 11.4.4 Page-Mode Support and Pipeline AccessesThe

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-37 11.4.5 Bank Interleaving The SDRAM interface suppo

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-38 Freescale Semiconductor Note that in 60x-compatible mode, the 60x address

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-39 • Last data out to precharge (P/LSDMR[LDOTOPRE]).

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-40 Freescale Semiconductor Figure 11-21. ACTTORW = 2 (2 Clock Cycles)11.4.6.3

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-41 11.4.6.4 Last Data Out to Precharge As shown in Fi

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xliv Freescale Semiconductor ContentsParagraphNumber TitlePageNumber

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-42 Freescale Semiconductor 11.4.6.6 Refresh Recovery Interval (RFRC)As repres

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-43 P/LSDMR[BUFCMD] should be set. Setting this bit ca

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-44 Freescale Semiconductor Figure 11-29. SDRAM Single-Beat Read, Page Hit, CL

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-45 Figure 11-32. SDRAM Single-Beat Write, Page HitFig

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-46 Freescale Semiconductor Figure 11-35. SDRAM Write-after-Write Pipelined, P

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-47 11.4.9 SDRAM MODE-SET Command TimingThe PowerQUICC

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-48 Freescale Semiconductor There are two levels of refresh request priority—l

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-49 11.4.12.1 SDRAM Configuration Example (Page-Based

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-50 Freescale Semiconductor Because AP alternates with A[7] of the row lines,

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-51 Now, from the SDRAM device point of view, during a

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xlv FiguresFigureNumber TitlePageNumber1-1 PowerQUICC II Block Diagram...

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-52 Freescale Semiconductor The GPCM allows a glueless and flexible interface

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-53 11.5.1 Timing ConfigurationIf BRx[MS] selects the

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-54 Freescale Semiconductor • One quarter of a clock cycle later• One half of

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-55 Figure 11-43. GPCM Memory Device InterfaceAs Figur

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-56 Freescale Semiconductor Figure 11-45. GPCM Memory Device Basic Timing (ACS

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-57 Figure 11-47. GPCM Relaxed-Timing Write (ACS = 1x

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-58 Freescale Semiconductor Figure 11-49. GPCM Relaxed-Timing Write (ACS = 00

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-59 11.5.1.6 Extended Hold Time on Read AccessesSlow m

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-60 Freescale Semiconductor Figure 11-51. GPCM Read Followed by Read (ORx[29–

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-61 Figure 11-53. GPCM Read Followed by Write (ORx[29

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xlvi Freescale Semiconductor FiguresFigureNumber TitlePageNumber4-19 Interrupt Table Handling Exa

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-62 Freescale Semiconductor Figure 11-54. External Termination of GPCM Access1

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-63 11.5.4 Differences between MPC8xx’s GPCM and MPC82

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-64 Freescale Semiconductor value driven on the external memory controller pin

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-65 • Read burst cycle pattern (RBS)• Write single-bea

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-66 Freescale Semiconductor 11.6.1.1 Memory Access RequestsWhen an internal de

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-67 11.6.1.3 Software Requests—RUN CommandSoftware can

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-68 Freescale Semiconductor NOTEFor integer clock ratios, the widths of T1/2/3

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-69 Figure 11-60 shows how CSx, GPL1, and GPL2 can be

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-70 Freescale Semiconductor Figure 11-61. RAM Array and Signal Generation11.6.

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-71 Table 11-36 describes RAM word fields. Table 11-36

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xlvii FiguresFigureNumber TitlePageNumber8-9 28-Bit Extended Transfer to

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-72 Freescale Semiconductor 12 G1T1 General-purpose line 1 timing 1. Defines t

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-73 20 G5T1 General-purpose line 5 timing 1. Defines t

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-74 Freescale Semiconductor Additional information about some of the RAM word

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-75 Figure 11-63. CS Signal Selection11.6.4.1.2 Byte-S

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-76 Freescale Semiconductor 11.6.4.1.3 General-Purpose Signals (GxTx, GOx)The

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-77 11.6.4.2 Address Multiplexing The address lines ca

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-78 Freescale Semiconductor Figure 11-65. UPM Read Access Data Sampling11.6.4.

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-79 Figure 11-66. Wait Mechanism Timing for Internal a

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-80 Freescale Semiconductor This means that the address bus should be partitio

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-81 to logic 0) at the end of that cycle, unless there

Fast Ethernet Controller 35FCC HDLC Controller 36FCC Transparent Controller 37Serial Peripheral Interface (SPI) 38I2C Controller 39Parallel I/O Ports

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2xlviii Freescale Semiconductor FiguresFigureNumber TitlePageNumber9-36 PCI Bus Status Register ..

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-82 Freescale Semiconductor After timings are created, programming the UPM con

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-83 Figure 11-68. Single-Beat Read Access to FPM DRAMc

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-84 Freescale Semiconductor Figure 11-69. Single-Beat Write Access to FPM DRAM

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-85 Figure 11-70. Burst Read Access to FPM DRAM (No LO

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-86 Freescale Semiconductor Figure 11-71. Burst Read Access to FPM DRAM (LOOP)

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-87 Figure 11-72. Burst Write Access to FPM DRAM (No L

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-88 Freescale Semiconductor Figure 11-73. Refresh Cycle (CBR) to FPM DRAMcst1

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-89 Figure 11-74. Exception Cycle• If GPL_4 is not use

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-90 Freescale Semiconductor The timing diagram in Figure 11-75 shows how the b

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-91 Figure 11-75. FPM DRAM Burst Read Access (Data Sam

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor xlix FiguresFigureNumber TitlePageNumber9-77 Inbound Message Interrupt St

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-92 Freescale Semiconductor 11.7.0.1 EDO Interface ExampleFigure 11-76 shows a

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-93 Disable timer period MxMR[DSx]0b10Burst inhibit de

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-94 Freescale Semiconductor Figure 11-77. Single-Beat Read Access to EDO DRAMc

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-95 Figure 11-78. Single-Beat Write Access to EDO DRAM

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-96 Freescale Semiconductor Figure 11-79. Single-Beat Write Access to EDO DR

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-97 Figure 11-80. Burst Read Access to EDO DRAMcst1 00

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-98 Freescale Semiconductor Figure 11-81. Burst Write Access to EDO DRAMcst1 0

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-99 Figure 11-82. Refresh Cycle (CBR) to EDO DRAMcst1

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-100 Freescale Semiconductor Figure 11-83. Exception Cycle For EDO DRAMcst1 1

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-101 11.8 Handling Devices with Slow or Variable Acces

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2l Freescale Semiconductor FiguresFigureNumber TitlePageNumber11-22 CL = 2 (2 Clock Cycles) ...

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-102 Freescale Semiconductor There are two types of external bus masters:• Any

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-103 is sampled in the GPCM or after each READ/WRITE c

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-104 Freescale Semiconductor Figure 11-84. Pipelined Bus Operation and Memory

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 11-105 Figure 11-85. External Master Access (GPCM)11.9.5

Memory ControllerMPC8260 PowerQUICC II Family Reference Manual, Rev. 211-106 Freescale Semiconductor Figure 11-86. External Master Configuration with

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 12-1 Chapter 12 Secondary (L2) Cache SupportThe PowerQUICC II has featur

Secondary (L2) Cache SupportMPC8260 PowerQUICC II Family Reference Manual, Rev. 212-2 Freescale Semiconductor Figure 12-1. L2 Cache in Copy-Back Mode1

Secondary (L2) Cache SupportMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 12-3 mode sacrifices some of the write perfor

Secondary (L2) Cache SupportMPC8260 PowerQUICC II Family Reference Manual, Rev. 212-4 Freescale Semiconductor Figure 12-2. External L2 Cache in Write-

Secondary (L2) Cache SupportMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 12-5 In ECC/parity mode the L2 cache can supp

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor li FiguresFigureNumber TitlePageNumber11-63 CS Signal Selection...

Secondary (L2) Cache SupportMPC8260 PowerQUICC II Family Reference Manual, Rev. 212-6 Freescale Semiconductor Figure 12-3. External L2 Cache in ECC/Pa

Secondary (L2) Cache SupportMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 12-7 • BCR[L2D] = 0—L2 response time. In this

Secondary (L2) Cache SupportMPC8260 PowerQUICC II Family Reference Manual, Rev. 212-8 Freescale Semiconductor Figure 12-4. Read Access with L2 CacheCL

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 13-1 Chapter 13 IEEE 1149.1 Test Access PortThe PowerQUICC II provides a

IEEE 1149.1 Test Access PortMPC8260 PowerQUICC II Family Reference Manual, Rev. 213-2 Freescale Semiconductor Figure 13-1. Test Logic Block DiagramThe

IEEE 1149.1 Test Access PortMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 13-3 Figure 13-2. TAP Controller State Machin

IEEE 1149.1 Test Access PortMPC8260 PowerQUICC II Family Reference Manual, Rev. 213-4 Freescale Semiconductor Figure 13-3. Output Pin Cell (O.Pin)Figu

IEEE 1149.1 Test Access PortMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 13-5 Figure 13-5. Output Control Cell (IO.CTL

IEEE 1149.1 Test Access PortMPC8260 PowerQUICC II Family Reference Manual, Rev. 213-6 Freescale Semiconductor from the shift register to the parallel

IEEE 1149.1 Test Access PortMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 13-7 The parallel output of the instruction r

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lii Freescale Semiconductor FiguresFigureNumber TitlePageNumber14-8 Dual-Port RAM Memory Map...

IEEE 1149.1 Test Access PortMPC8260 PowerQUICC II Family Reference Manual, Rev. 213-8 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor IV-1 Part IVCommunications Processor ModuleIntended AudiencePart IV is in

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2IV-2 Freescale Semiconductor • Chapter 23, “SCC BISYNC Mode,” describes the PowerQUICC II impleme

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor IV-3 • Chapter 40, “Parallel I/O Ports,” describes the four general-purpo

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2IV-4 Freescale Semiconductor x In certain contexts, such as in a signal encoding or a bit field,

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor IV-5 Table IV-1. Acronyms and Abbreviated TermsTerm MeaningAAL ATM adapta

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2IV-6 Freescale Semiconductor GCRA Generic cell rate algorithm (leaky bucket)GPCM General-purpose

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor IV-7 PHY Physical layerPPM Pulse-position modulationRM Resource managemen

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2IV-8 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-1 Chapter 14 Communications Processor Module OverviewThe PowerQUICC I

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor liii FiguresFigureNumber TitlePageNumber17-2 Baud-Rate Generator Configur

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-2 Freescale Semiconductor — Synchronous UART (1x clock

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-3 Figure 14-1 shows the PowerQ

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-4 Freescale Semiconductor 14.3 Communications Processo

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-5 • 64-bit dual-port RAM acces

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-6 Freescale Semiconductor Figure 14-2. Communications

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-7 • Many parameters are exchan

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-8 Freescale Semiconductor 14.3.6 Execution from RAMThe

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-9 RCCR bit fields are describe

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-10 Freescale Semiconductor 12 EIE External interrupt e

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-11 14.3.8 RISC Time-Stamp Cont

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2liv Freescale Semiconductor FiguresFigureNumber TitlePageNumber21-5 Asynchronous UART Transmitter

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-12 Freescale Semiconductor After reset, setting RTSCR[

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-13 14.4.1 CP Command Register

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-14 Freescale Semiconductor 14.4.1.1 CP CommandsThe CP

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-15 Table 14-7. CP Command Opco

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-16 Freescale Semiconductor NOTEIf a reserved command i

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-17 14.4.2 Command Register Exa

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-18 Freescale Semiconductor Figure 14-7. Dual-Port RAM

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-19 Figure 14-8. Dual-Port RAM

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-20 Freescale Semiconductor unused parameter RAM, such

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-21 Table 14-10. Parameter RAMP

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lv FiguresFigureNumber TitlePageNumber25-4 Ethernet Address Recognition F

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-22 Freescale Semiconductor 14.6 RISC Timer TablesThe C

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-23 Figure 14-9. RISC Timer Tab

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-24 Freescale Semiconductor 14.6.2 RISC Timer Command R

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-25 14.6.5 SET TIMER CommandThe

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-26 Freescale Semiconductor 14.6.7 RISC Timer Initializ

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 14-27 If a SET TIMER command is i

Communications Processor Module OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 214-28 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-1 Chapter 15 Serial Interface with Time-Slot AssignerFigure 15-1 show

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-2 Freescale Semiconductor Figure 15-1. SI Block Diagra

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-3 15.1 FeaturesEach SI has the

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lvi Freescale Semiconductor FiguresFigureNumber TitlePageNumber28-14 Transmitter Super Channel Ex

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-4 Freescale Semiconductor • Independent mapping for re

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-5 Figure 15-2. Various Configu

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-6 Freescale Semiconductor At its most flexible, the TS

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-7 to program the receive routi

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-8 Freescale Semiconductor Figure 15-4. Enabling Connec

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-9 15.4.1 One Multiplexed Chann

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-10 Freescale Semiconductor Figure 15-6. One TDM Channe

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-11 Table 15-1. SIx RAM Entry (

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-12 Freescale Semiconductor Figure 15-8 shows how SWTR

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-13 Table 15-2. SIx RAM Entry (

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lvii FiguresFigureNumber TitlePageNumber30-22 VCI Filtering Enable Bits .

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-14 Freescale Semiconductor 15.4.4 SIx RAM Programming

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-15 • Static routing. The numbe

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-16 Freescale Semiconductor Figure 15-9. Example: SIx R

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-17 15.5 Serial Interface Regis

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-18 Freescale Semiconductor Table 15-5 describes SIxMR

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-19 6–7 RFSDx Receive frame syn

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-20 Freescale Semiconductor Figure 15-12 shows the one-

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-21 Figure 15-14. Falling Edge

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-22 Freescale Semiconductor Figure 15-16. Falling Edge

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-23 Figure 15-17. Falling Edge

35 Fast Ethernet Controller36 FCC HDLC Controller37 FCC Transparent Controller38 Serial Peripheral Interface (SPI)39 I2C Controller40 Parallel I/O Po

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lviii Freescale Semiconductor FiguresFigureNumber TitlePageNumber30-63 COMM_INFO Field ...

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-24 Freescale Semiconductor Table 15-6. describes SIxRS

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-25 15.5.5 SI Status Registers

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-26 Freescale Semiconductor (physical layer device) and

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-27 Figure 15-22. IDL Terminal

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-28 Freescale Semiconductor The basic rate IDL bus has

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-29 device negates L1GRx. The P

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-30 Freescale Semiconductor 2. CMXSI1CR = 0x00. TDMA re

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-31 The GCI bus consists of fou

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-32 Freescale Semiconductor • M is a 64-Kbps monitor ch

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 15-33 signals to the SIx RAM tran

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lix FiguresFigureNumber TitlePageNumber32-7 CPS Tx Queue Descriptor (TxQD

Serial Interface with Time-Slot AssignerMPC8260 PowerQUICC II Family Reference Manual, Rev. 215-34 Freescale Semiconductor NOTEIf SCIT mode is not use

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 16-1 Chapter 16 CPM MultiplexingThe CPM multiplexing logic (CMX) connect

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 216-2 Freescale Semiconductor Figure 16-1. CPM Multiplexing Logic (CMX) Block Diag

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 16-3 • Each SCC can have its own set of modem control pin

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 216-4 Freescale Semiconductor Figure 16-2. Enabling Connections to the TSA16.3 NMS

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 16-5 Figure 16-3. Bank of ClocksThe eight BRGs also make

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 216-6 Freescale Semiconductor Table 16-1. Clock Source OptionsClockCLK BRG12345678

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 16-7 NOTEAfter a clock source is selected, the clock is g

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 216-8 Freescale Semiconductor NOTEEach SADx and MADx corresponds to a pair of sepa

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 16-9 Figure 16-5. Connection of the Master Address• For s

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lx Freescale Semiconductor FiguresFigureNumber TitlePageNumber33-23 IMA Transmit Interrupt Status

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 216-10 Freescale Semiconductor NOTEThe user must program the addresses of the PHYs

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 16-11 Figure 16-7. Multi-PHY Receive Address Multiplexing

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 216-12 Freescale Semiconductor 16.4.2 CMX SI1 Clock Route Register (CMXSI1CR)The C

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 16-13 Table 16-4 describes CMXSI2CR fields.16.4.4 CMX FCC

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 216-14 Freescale Semiconductor Table 16-5 describes CMXFCR fields.0 1 2 4 5 7 8 9

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 16-15 8-9 FC2 Defines the FCC2 connection.00 FCC2 is not

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 216-16 Freescale Semiconductor 16.4.5 CMX SCC Clock Route Register (CMXSCR)The CMX

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 16-17 2–4 RS1CS Receive SCC1 clock source (NMSI mode). Ig

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 216-18 Freescale Semiconductor 17 SC3 SCC3 connection0 SCC3 is not connected to th

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 16-19 16.4.6 CMX SMC Clock Route Register (CMXSMR)The CMX

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxi FiguresFigureNumber TitlePageNumber36-9 FCC Status Register (FCCS)...

CPM MultiplexingMPC8260 PowerQUICC II Family Reference Manual, Rev. 216-20 Freescale Semiconductor 2–3 SMC1CS SMC1 clock source (NMSI mode). SMC1 can

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 17-1 Chapter 17 Baud-Rate Generators (BRGs)The CPM contains eight indepe

Baud-Rate Generators (BRGs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 217-2 Freescale Semiconductor source for multiple BRGs. The external so

Baud-Rate Generators (BRGs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 17-3 Table 17-2 shows the possible external cl

Baud-Rate Generators (BRGs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 217-4 Freescale Semiconductor 17.2 Autobaud Operation on a UARTDuring t

Baud-Rate Generators (BRGs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 17-5 17.3 UART Baud Rate Examples For synchron

Baud-Rate Generators (BRGs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 217-6 Freescale Semiconductor For example, to get a rate of 64 kbps, th

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 18-1 Chapter 18 TimersThe CPM includes four identical 16-bit general-pur

TimersMPC8260 PowerQUICC II Family Reference Manual, Rev. 218-2 Freescale Semiconductor • 16-nanosecond resolution (at 66 MHz)• Programmable sources f

TimersMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 18-3 The restart gate mode performs the same function as normal mod

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxii Freescale Semiconductor FiguresFigureNumber TitlePageNumber

TimersMPC8260 PowerQUICC II Family Reference Manual, Rev. 218-4 Freescale Semiconductor Table 18-1 describes TGCR1 fields.The TGCR2 register is shown

TimersMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 18-5 Table 18-2 describes TGCR2 fields.18.2.3 Timer Mode Registers

TimersMPC8260 PowerQUICC II Family Reference Manual, Rev. 218-6 Freescale Semiconductor Table 18-3 describes TMR1–TMR4 register fields.18.2.4 Timer Re

TimersMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 18-7 18.2.5 Timer Capture Registers (TCR1–TCR4)Each timer capture r

TimersMPC8260 PowerQUICC II Family Reference Manual, Rev. 218-8 Freescale Semiconductor Writing ones clears event bits; writing zeros has no effect. B

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-1 Chapter 19 SDMA Channels and IDMA EmulationThe PowerQUICC II has tw

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-2 Freescale Semiconductor The SDMA channel can be assigned big

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-3 Figure 19-2. SDMA Bus Arbitration (T

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-4 Freescale Semiconductor 19.2.2 SDMA Mask Register (SDMR)The

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-5 19.3 IDMA EmulationThe CPM can be co

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxiii TablesTableNumber TitlePageNumberi Changes to MPC8260 Family Refere

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-6 Freescale Semiconductor • Programmable byte-order conversion

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-7 Figure 19-5 shows the IDMA transfer

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-8 Freescale Semiconductor Figure 19-6. Example IDMA Transfer B

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-9 19.5.1.2 Normal ModeWhen external re

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-10 Freescale Semiconductor Any IDMA access to a peripheral use

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-11 related to the dual-port RAM bus ar

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-12 Freescale Semiconductor Conversely, if the transfer size is

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-13 19.6 IDMA PrioritiesEach IDMA chann

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-14 Freescale Semiconductor DREQx may be configured as either e

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-15 Figure 19-7. Timing Requirement for

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxiv Freescale Semiconductor TablesTableNumber TitlePageNumber4-23 PITR Field Descriptions...

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-16 Freescale Semiconductor NOTEWhen DREQ is level-sensitive an

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-17 Figure 19-8. IDMAx Channel’s BD Tab

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-18 Freescale Semiconductor Table 19-4. IDMAx Parameter RAMOffs

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-19 19.8.2.1 DMA Channel Mode (DCM)The

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-20 Freescale Semiconductor Table 19-5. DCM Field DescriptionsB

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-21 19.8.2.2 Data Transfer Types as Pro

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-22 Freescale Semiconductor 19.8.2.3 Programming DTS and STSThe

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-23 Table 19-8 describes valid STS/DTS

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-24 Freescale Semiconductor transfer sizes allows longer transf

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-25 Table 19-10 describes IDMA BD field

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxv TablesTableNumber TitlePageNumber9-16 PITARx Field Descriptions...

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-26 Freescale Semiconductor 6 CM Continuous mode0 Buffer chaini

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-27 19.9 IDMA CommandsThe user has two

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-28 Freescale Semiconductor In external request mode (ERM=1), t

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-29 19.10.1 Externally Recognizing IDMA

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-30 Freescale Semiconductor Table 19-14 describes parallel I/O

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-31 DCM(SINC) = 0 The peripheral addres

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-32 Freescale Semiconductor 19.12.2 Memory-to-Peripheral Fly-By

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 19-33 19.12.3 Memory-to-Memory (PCI Bus t

SDMA Channels and IDMA EmulationMPC8260 PowerQUICC II Family Reference Manual, Rev. 219-34 Freescale Semiconductor DCM[DINC] = 1 The destination memor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-1 Chapter 20 Serial Communications Controllers (SCCs)The PowerQUICC I

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxvi Freescale Semiconductor TablesTableNumber TitlePageNumber9-57 OPTPR Field Descriptions...

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-2 Freescale Semiconductor Figure 20-1. SCC Block Diagr

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-3 • Fully transparent option f

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-4 Freescale Semiconductor 19–20 TRX, TTXTransparent re

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-5 Figure 20-3 shows GSMR_L.Tab

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-6 Freescale Semiconductor 1–2 EDGE Clock edge. Determi

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-7 11–12 TPP Tx preamble patter

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-8 Freescale Semiconductor 24–25 DIAG Diagnostic mode.

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-9 20.1.2 Protocol-Specific Mod

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-10 Freescale Semiconductor 20.1.4 Transmit-on-Demand R

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-11 — For an RxBD, this is the

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxvii TablesTableNumber TitlePageNumber11-21 SDRAM Address Multiplexing (

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-12 Freescale Semiconductor Figure 20-7. SCC BD and Buf

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-13 20.3 SCC Parameter RAMEach

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-14 Freescale Semiconductor 20.3.1 SCC Base AddressesTh

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-15 20.3.2 Function Code Regist

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-16 Freescale Semiconductor 20.3.3 Handling SCC Interru

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-17 Additional information abou

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-18 Freescale Semiconductor Figure 20-9. Output Delay f

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-19 Figure 20-11. CTS Lost in S

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-20 Freescale Semiconductor Figure 20-12. Using CD to C

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-21 20.3.6 Digital Phase-Locked

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor v ContentsParagraphNumber TitlePageNumberAbout This BookReference Manual

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxviii Freescale Semiconductor TablesTableNumber TitlePageNumber15-4 SIxGMR Field Descriptions...

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-22 Freescale Semiconductor Figure 20-14. DPLL Transmit

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-23 The DPLL can also be used t

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-24 Freescale Semiconductor If the DPLL is not needed,

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 20-25 4. If an INIT TX PARAMETERS

Serial Communications Controllers (SCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 220-26 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-1 Chapter 21 SCC UART ModeThe universal asynchronous receiver transmi

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-2 Freescale Semiconductor In synchronous UART (isochronous operation), a separate

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-3 3. Address/data bit (optional)4. Parity bit (optional)5

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-4 Freescale Semiconductor Table 21-1. UART-Specific SCC Parameter RAM Memory MapO

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-5 21.5 Data-Handling Methods: Character- or Message-Based

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxix TablesTableNumber TitlePageNumber20-2 GSMR_L Field Descriptions ...

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-6 Freescale Semiconductor 21.7 SCC UART CommandsThe transmit commands in Table 21

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-7 • Automatic multidrop mode—The controller checks the in

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-8 Freescale Semiconductor Table 21-4 describes the data structure used in control

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-9 21.10 Hunt Mode (Receiver)A UART receiver in hunt mode

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-10 Freescale Semiconductor 21.12 Sending a Break (Transmitter)A break is an all-z

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-11 21.15 Handling Errors in the SCC UART ControllerThe UA

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-12 Freescale Semiconductor 21.16 UART Mode Register (PSMR)For UART mode, the SCC

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-13 Table 21-9 describes PSMR UART fields.0 1 2 3 4 5 6 7

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-14 Freescale Semiconductor 21.17 SCC UART Receive Buffer Descriptor (RxBD)The CPM

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-15 •An ENTER HUNT MODE or CLOSE RXBD command is issued.•

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxx Freescale Semiconductor TablesTableNumber TitlePageNumber23-10 PSMR Field Descriptions...

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-16 Freescale Semiconductor Figure 21-7. SCC UART Receiving using RxBDsFigure 21-8

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-17 Table 21-10 describes RxBD status and control fields.0

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-18 Freescale Semiconductor Section 20.2, “SCC Buffer Descriptors (BDs),” describe

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-19 The data length and buffer pointer fields are describe

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-20 Freescale Semiconductor Figure 21-10. SCC UART Interrupt Event ExampleSCCE bit

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-21 21.20 SCC UART Status Register (SCCS)The SCC UART stat

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-22 Freescale Semiconductor 21.21 SCC UART Programming ExampleThe following initia

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 21-23 18. Initialize the TxBD. Assume the buffer is at 0x000

SCC UART ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 221-24 Freescale Semiconductor To receive S-records, the core must wait for an RX int

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-1 Chapter 22 SCC HDLC ModeHigh-level data link control (HDLC) is one

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxxi TablesTableNumber TitlePageNumber27-17 SMC GCI Parameter RAM Memory

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-2 Freescale Semiconductor • Four address comparison registers with mask• Maintena

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-3 and an address mask. The SCC compares the received addr

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-4 Freescale Semiconductor Figure 22-2 shows 16- and 8-bit address recognition. Fi

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-5 address comparisons. Receive errors are reported throug

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-6 Freescale Semiconductor Reception errors are described in Table 22-5. Table 22-

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-7 22.8 HDLC Mode Register (PSMR)The protocol-specific mod

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-8 Freescale Semiconductor 22.9 SCC HDLC Receive Buffer Descriptor (RxBD)The CP us

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-9 Data length and buffer pointer fields are described in

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-10 Freescale Semiconductor Figure 22-5. SCC HDLC Receiving Using RxBDsBuffer00x00

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-11 22.10 SCC HDLC Transmit Buffer Descriptor (TxBD)The CP

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxxii Freescale Semiconductor TablesTableNumber TitlePageNumber30-7 Fields and their Positions in

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-12 Freescale Semiconductor The data length and buffer pointer fields are describe

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-13 Figure 22-8 shows interrupts that can be generated usi

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-14 Freescale Semiconductor 22.12 SCC HDLC Status Register (SCCS)The SCC status re

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-15 3. Configure port C pin 29 to enable the CLK3 pin. Set

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-16 Freescale Semiconductor 25. Write 0x0000 to PSMR2 to configure one opening and

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-17 transmission continues. If the echo bit is ever 0 when

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-18 Freescale Semiconductor In single-master configuration, a master station trans

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-19 While in the active condition (ready to transmit), the

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-20 Freescale Semiconductor Figure 22-13. Nonsymmetrical Tx Clock Duty Cycle for I

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 22-21 Figure 22-15. Delayed RTS Mode22.15.5 Using the Time-S

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxxiii TablesTableNumber TitlePageNumber30-48 FCCE/FCCM Field Description

SCC HDLC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 222-22 Freescale Semiconductor 22.15.6 HDLC Bus Protocol ProgrammingThe HDLC bus on t

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 23-1 Chapter 23 SCC BISYNC ModeThe byte-oriented BISYNC protocol was dev

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 223-2 Freescale Semiconductor 23.1 FeaturesThe following list summarizes features o

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 23-3 23.3 SCC BISYNC Channel Frame ReceptionAlthough the r

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 223-4 Freescale Semiconductor GSMR[MODE] determines the protocol for each SCC. The

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 23-5 Receive commands are described in Table 23-3.23.6 SCC

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 223-6 Freescale Semiconductor The control character table lets the BISYNC controlle

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 23-7 23.7 BISYNC SYNC Register (BSYNC)The BSYNC register,

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 223-8 Freescale Semiconductor 23.8 SCC BISYNC DLE Register (BDLE)Seen in Figure 23-

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 23-9 23.9 Sending and Receiving the Synchronization Sequen

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxxiv Freescale Semiconductor TablesTableNumber TitlePageNumber33-9 ICP Cell Template ...

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 223-10 Freescale Semiconductor Table 23-9 describes receive errors. 23.11 BISYNC Mo

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 23-11 Table 23-10. PSMR Field DescriptionsBits Name Descri

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 223-12 Freescale Semiconductor 23.12 SCC BISYNC Receive BD (RxBD)The CP uses BDs to

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 23-13 Data length and buffer pointer fields are described

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 223-14 Freescale Semiconductor 23.13 SCC BISYNC Transmit BD (TxBD)The CP arranges d

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 23-15 Data length and buffer pointer fields are described

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 223-16 Freescale Semiconductor Table 23-13 describes SCCE and SCCM fields.23.15 SCC

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 23-17 23.16 Programming the SCC BISYNC ControllerSoftware

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 223-18 Freescale Semiconductor After ETX, a BCS is expected; then the buffer should

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 23-19 17. Write CHARACTER2–8 with 0x8000. They are not use

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxxv TablesTableNumber TitlePageNumber35-9 FCCE/FCCM Field Descriptions..

SCC BISYNC ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 223-20 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 24-1 Chapter 24 SCC Transparent ModeTransparent mode (also called totall

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 224-2 Freescale Semiconductor 24.2 SCC Transparent Channel Frame Transmission

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 24-3 24.4 Achieving Synchronization in Transparent Mo

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 224-4 Freescale Semiconductor frame. Pulse operation allows an uninterrupted s

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 24-5 24.4.1.3 Transparent Mode without Explicit Synch

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 224-6 Freescale Semiconductor 24.5 CRC Calculation in Transparent ModeThe CRC

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 24-7 Table 24-4 describes receive commands.24.8 Handl

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 224-8 Freescale Semiconductor 24.9 Transparent Mode and the PSMRThe protocol-s

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 24-9 Table 24-7. SCC Transparent RxBD Status and Cont

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxxvi Freescale Semiconductor TablesTableNumber TitlePageNumberA-2 User-Level PowerPC SPRs ...

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 224-10 Freescale Semiconductor Data length and buffer pointer fields are descr

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 24-11 Data length and buffer pointer fields are descr

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 224-12 Freescale Semiconductor 24.13 SCC Status Register in Transparent Mode (

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 24-13 The transmit and receive clocks are externally

SCC Transparent ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 224-14 Freescale Semiconductor NOTEAfter 5 bytes are sent, the Tx buffer is cl

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-1 Chapter 25 SCC Ethernet ModeThe Ethernet IEEE 802.3 protocol is a w

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-2 Freescale Semiconductor Figure 25-2. Ethernet Block DiagramThe PowerQUICC I

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-3 — Two nonaggressive backoff modes— Automatic frame

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-4 Freescale Semiconductor 25.3 Connecting the PowerQUICC II to EthernetThe ba

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-5 connect to AUI or twisted-pair media are external t

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxxvii About This BookThe primary objective of this manual is to help com

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-6 Freescale Semiconductor 25.5 SCC Ethernet Channel Frame Reception The Ether

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-7 generate writes to the CAM for address recognition.

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-8 Freescale Semiconductor 0x4C MINFLR Hword Minimum frame length register. Th

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-9 25.8 Programming the Ethernet ControllerThe core co

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-10 Freescale Semiconductor Table 25-3 describes receive commands.NOTEAfter a

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-11 25.10 SCC Ethernet Address RecognitionThe Ethernet

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-12 Freescale Semiconductor address, address recognition can be performed on m

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-13 If a collision occurs within 64 byte times, the re

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-14 Freescale Semiconductor Table 25-5 describes reception errors.25.17 Ethern

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-15 Table 25-6. PSMR Field DescriptionsBits Name Descr

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2vi Freescale Semiconductor ContentsParagraphNumber TitlePageNumber1.7.2.5 PCI with 155-Mbps ATM..

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxxviii Freescale Semiconductor UsSome descriptions in this manual pertain only to specific devic

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-16 Freescale Semiconductor 25.18 SCC Ethernet Receive BDThe Ethernet controll

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-17 Data length and buffer pointer fields are describe

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-18 Freescale Semiconductor Figure 25-7. Ethernet Receiving using RxBDs25.19 S

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-19 Table 25-8 describes TxBD status and control field

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-20 Freescale Semiconductor Data length and buffer pointer fields are describe

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-21 Figure 25-10 shows an example of interrupts that c

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-22 Freescale Semiconductor 25.21 SCC Ethernet Programming ExampleThe followin

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 25-23 23. Write 0x0040_0000 to the SIU interrupt mask re

SCC Ethernet ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 225-24 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 26-1 Chapter 26 SCC AppleTalk ModeAppleTalk is a set of protocols develo

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxxix Before Using this Manual—Important NoteBefore using this manual, de

SCC AppleTalk ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 226-2 Freescale Semiconductor RTS pin) is sent to request the network, a CTS fra

SCC AppleTalk ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 26-3 Figure 26-2. Connecting the PowerQUICC II to Local

SCC AppleTalk ModeMPC8260 PowerQUICC II Family Reference Manual, Rev. 226-4 Freescale Semiconductor 8. Clear TINV and RINV so data will not be inverte

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-1 Chapter 27 Serial Management Controllers (SMCs)The two serial manag

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-2 Freescale Semiconductor The receive data source can be L

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-3 Table 27-1 describes SMCMR field

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-4 Freescale Semiconductor 27.2.2 SMC Buffer Descriptor Ope

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-5 Figure 27-3. SMC Memory Structur

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-6 Freescale Semiconductor Table 27-2. SMC UART and Transpa

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-7 To extract data from a partially

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxxx Freescale Semiconductor • Part III, “The Hardware Interface,” describes external signals, cl

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-8 Freescale Semiconductor 27.2.3.1 SMC Function Code Regis

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-9 27.2.4.1 SMC Transmitter Full Se

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-10 Freescale Semiconductor 2. Issue an INIT TX AND RX PARA

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-11 27.3.1 FeaturesThe following li

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-12 Freescale Semiconductor errors are reported via the BDs

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-13 number of break characters acco

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-14 Freescale Semiconductor • A programmable number of cons

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-15 Data length represents the numb

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-16 Freescale Semiconductor Figure 27-7. RxBD ExampleByte 5

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-17 27.3.10 SMC UART TxBDData is se

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxxxi — Chapter 22, “SCC HDLC Mode,” describes the PowerQUICC II implemen

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-18 Freescale Semiconductor to 3. To send three UART charac

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-19 Figure 27-10. SMC UART Interrup

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-20 Freescale Semiconductor 12. Initialize the RxBD. Assume

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-21 • Transmits and receives transp

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-22 Freescale Semiconductor SMC continues transferring data

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-23 Figure 27-11. Synchronization w

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-24 Freescale Semiconductor Figure 27-12. Synchronization w

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-25 describes how to safely disable

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-26 Freescale Semiconductor 27.4.8 SMC Transparent RxBDUsin

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-27 Data length and buffer pointer

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxxxii Freescale Semiconductor MC68360, the MC68302, the M68HC11, and M68HC05 microcontroller fam

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-28 Freescale Semiconductor Data length represents the numb

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-29 Table 27-16 describes SMCE/SMCM

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-30 Freescale Semiconductor 8. Write MRBLR with the maximum

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-31 27.5.2 Handling the GCI Monitor

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-32 Freescale Semiconductor 27.5.3 Handling the GCI C/I Cha

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-33 27.5.6 SMC GCI Monitor Channel

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-34 Freescale Semiconductor Table 27-21 describes SMC C/I c

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 27-35 the internal interrupt request

Serial Management Controllers (SMCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 227-36 Freescale Semiconductor

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-1 Chapter 28 Multi-Channel Controllers (MCCs)NOTEThe MPC8250 and the

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxxxiii • Application notes—These short documents contain useful informat

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-2 Freescale Semiconductor • Efficient control of the interrupt

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-3 — Section 28.3.4, “Channel-Specific

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-4 Freescale Semiconductor 28.2 Global MCC ParametersThe global

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-5 28.3 Channel-Specific ParametersEach

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-6 Freescale Semiconductor Table 28-2. Channel-Specific Paramet

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-7 28.3.1.1 Internal Transmitter State

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-8 Freescale Semiconductor 28.3.1.2 Interrupt Mask (INTMSK)—HDL

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-9 Table 28-4. CHAMR Field Descriptions

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-10 Freescale Semiconductor 28.3.1.4 Internal Receiver State (R

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-11 28.3.2 Channel-Specific Transparent

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxxxiv Freescale Semiconductor BIST Built-in self testBPU Branch processing unitBRI Basic rate in

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-12 Freescale Semiconductor 28.3.2.1 Internal Transmitter State

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-13 28.3.2.3 Channel Mode Register (CHA

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-14 Freescale Semiconductor 28.3.2.4 Internal Receiver State (R

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-15 28.3.3.1 Channel-Specific Parameter

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-16 Freescale Semiconductor The CHAMR in CES mode fields are de

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-17 28.3.4 Channel-Specific SS7 Paramet

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-18 Freescale Semiconductor • Flow controlSS7 features are as f

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-19 Table 28-10. Channel-Specific Param

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-20 Freescale Semiconductor 0x38 MFLR Hword Maximum frame lengt

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-21 28.3.4.1 Extended Channel Mode Regi

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxxxv IEEE Institute of Electrical and Electronics EngineersIrDA Infrared

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-22 Freescale Semiconductor ECHAMR fields are described in Tabl

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-23 28.3.4.2 Signal Unit Error Monitor

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-24 Freescale Semiconductor • For every JTRDelay an error flag

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-25 28.3.4.3.1 AERM ImplementationThe S

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-26 Freescale Semiconductor To disable AERM and enter SUERM, do

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-27 • State 0—The first 3-5 bytes (depe

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-28 Freescale Semiconductor 28.3.4.5 Octet Counting Mode—SS7 Mo

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-29 28.5 SuperchannelsA TDM may not be

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-30 Freescale Semiconductor 28.5.2 Superchannels and Receiving

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-31 Figure 28-14. Transmitter Super Cha

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxxxvi Freescale Semiconductor SCC Serial communication controllerSCP Serial control portSDLC Syn

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-32 Freescale Semiconductor of the managing MCC channel for tha

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-33 Figure 28-16. Receiver Super Channe

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-34 Freescale Semiconductor Table 28-16 describes group assignm

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-35 28.8 MCC ExceptionsThe MCC interrup

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-36 Freescale Semiconductor Event Register (MCCE)/Mask Register

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-37 desired interrupt handler latency o

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-38 Freescale Semiconductor 28.8.1.1 Interrupt Circular Table E

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-39 Table 28-19. Interrupt Circular Tab

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-40 Freescale Semiconductor 28.8.1.2 Global Transmitter Underru

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-41 To avoid these cases, pad out the S

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor lxxxvii PowerPC Architecture Terminology ConventionsTable iv lists certai

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-42 Freescale Semiconductor 28.8.1.2.6 CPM PriorityIt is possib

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-43 28.8.1.4 Global Overrun (GOV)An MCC

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-44 Freescale Semiconductor Table 28-22. RxBD Field Description

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-45 The data length and buffer pointer

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-46 Freescale Semiconductor Table 28-23 describes TxBD fields.0

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-47 The data length and buffer pointer

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-48 Freescale Semiconductor 3. Program the SI’s SIRAM and relat

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 28-49 The following sequence must be foll

Multi-Channel Controllers (MCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 228-50 Freescale Semiconductor If multiple synchronized TDMs are u

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-1 Chapter 29 Fast Communications Controllers (FCCs)NOTEThe MPC8255 ha

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor vii ContentsParagraphNumber TitlePageNumber2.5.1 PowerPC Exception Model.

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2lxxxviii Freescale Semiconductor

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-2 Freescale Semiconductor ATM interfaces (UTOPIA); see C

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-3 Figure 29-1. FCC Block Diagram

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-4 Freescale Semiconductor Table 29-2. describes GFMR fie

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-5 3 TRX Transparent receiver. Th

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-6 Freescale Semiconductor 8 CTSS CTS sampling0 The CTS i

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-7 NOTEIn addition to selecting t

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-8 Freescale Semiconductor 29.4 FCC Data Synchronization

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-9 Fields in the FTODR are descri

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-10 Freescale Semiconductor Figure 29-5. FCC Memory Struc

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-11 The CP processes the TxBDs in

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor I-1 Part IOverviewIntended AudiencePart I is intended for readers who nee

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-12 Freescale Semiconductor • See Section 29.12, “Disabli

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-13 29.7.1 FCC Function Code Regi

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-14 Freescale Semiconductor 29.8 Interrupts from the FCCs

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-15 no effect on bit values. FCCE

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-16 Freescale Semiconductor The first RxBD’s empty bit mu

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-17 6. Enable FCC transmission by

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-18 Freescale Semiconductor Figure 29-8. Output Delay fro

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-19 Figure 29-10. CTS LostNOTEIf

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-20 Freescale Semiconductor Figure 29-11. Using CD to Con

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 29-21 29.12.1 FCC Transmitter Full

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2I-2 Freescale Semiconductor Acronyms and AbbreviationsTable I-1 contains acronyms and abbreviatio

Fast Communications Controllers (FCCs)MPC8260 PowerQUICC II Family Reference Manual, Rev. 229-22 Freescale Semiconductor 2. Issue the INIT RX PARAMETE

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-1 Chapter 30 ATM Controller and AAL0, AAL1, and AAL5NOTEThe functiona

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-2 Freescale Semiconductor • Up to 255 active VCs intern

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-3 – Sequence number generation–

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-4 Freescale Semiconductor — Performs ATMF UNI 4.0 ABR f

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-5 30.2.1 Transmitter OverviewBe

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-6 Freescale Semiconductor For the structured format, th

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-7 (UDC mode) include an extra h

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-8 Freescale Semiconductor The PowerQUICC II supports pa

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-9 For information about cell ra

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor I-3 MII Media-independent interfaceMMU Memory management unitMSR Machine

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-10 Freescale Semiconductor Each 2-byte time-slot entry

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-11 For the above example, 32 k

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-12 Freescale Semiconductor 30.3.5.3 Peak and Sustain Tr

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-13 Equation D yields the number

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-14 Freescale Semiconductor 30.4.1 External CAM LookupAn

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-15 30.4.2 Address CompressionTh

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-16 Freescale Semiconductor to indicate the received cel

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-17 The PowerQUICC II can check

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-18 Freescale Semiconductor Figure 30-8 shows the VC poi

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-19 Figure 30-9. ATM Address Rec

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2I-4 Freescale Semiconductor

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-20 Freescale Semiconductor support. The destination rec

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-21 7. Before sending an F-RM ce

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-22 Freescale Semiconductor Figure 30-11. ABR Transmit F

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-23 Figure 30-12. ABR Transmit F

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-24 Freescale Semiconductor Figure 30-13. ABR Transmit F

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-25 Figure 30-14. ABR Receive Fl

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-26 Freescale Semiconductor 30.5.2.1 RM Cell Rate Repres

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-27 30.5.3 ABR Flow Control Setu

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-28 Freescale Semiconductor 30.6.2 Virtual Path (F4) Flo

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-29 insert it in an AAL0 TxBD. F

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-1 Chapter 1 OverviewThe PowerQUICC II™ is a versatile communications p

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-30 Freescale Semiconductor 30.6.6.1 Running a Performan

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-31 Before the BRC is transferre

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-32 Freescale Semiconductor 30.6.6.4 BRC Performance Cal

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-33 30.8 ATM Layer StatisticsAT

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-34 Freescale Semiconductor Figure 30-21. ATM-to-TDM Int

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-35 30.9.3 Timing IssuesUse of t

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-36 Freescale Semiconductor The MCC and ATM controller s

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-37 0x44 UDC_TMP_BASE Hword UDC

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-38 Freescale Semiconductor 0x78 VPT1_BASE / EXT_CAM1_BA

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-39 30.10.1.1 Determining UEAD_O

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-2 Freescale Semiconductor — Floating-point unit (FPU) supports floating-point arithmeti

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-40 Freescale Semiconductor 30.10.1.3 Global Mode Entry

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-41 30.10.2 Connection Tables (R

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-42 Freescale Semiconductor a VC when sending a ATM TRAN

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-43 Table 30-16 describes RCT fi

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-44 Freescale Semiconductor Table 30-16. RCT Field Descr

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-45 30.10.2.2.1 AAL5 Protocol-Sp

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-46 Freescale Semiconductor Table 30-17 describes AAL5 p

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-47 Table 30-18 describes AAL5-A

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-48 Freescale Semiconductor Table 30-19. AAL1 Protocol-S

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-49 30.10.2.2.4 AAL0 Protocol-Sp

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-3 — Three user programmable machines, general-purpose chip-sele

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-50 Freescale Semiconductor 30.10.2.2.5 AAL1 CES Protoco

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-51 Table 30-21 describes genera

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-52 Freescale Semiconductor

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-53 Table 30-21. TCT Field Descr

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-54 Freescale Semiconductor 0x02 0 — Internal use only.

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-55 30.10.2.3.1 AAL5 Protocol-Sp

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-56 Freescale Semiconductor Table 30-23 describes AAL1 p

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-57 30.10.2.3.3 AAL0 Protocol-Sp

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-58 Freescale Semiconductor Table 30-25 describes VBR pr

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-59 Table 30-26 describes UBR+ p

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 21-4 Freescale Semiconductor – Transparent– UART (low-speed operation)— One serial periphe

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-60 Freescale Semiconductor Table 30-27 describes ABR-sp

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-61 3 NI-TA No increase–turn-aro

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-62 Freescale Semiconductor 30.10.3 OAM Performance Moni

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-63 30.10.4 APC Data StructureTh

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-64 Freescale Semiconductor Figure 30-38. ATM Pace Contr

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-65 30.10.4.2 APC Priority Table

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-66 Freescale Semiconductor Table 30-31 describes contro

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-67 Figure 30-41. Transmit Buff

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-68 Freescale Semiconductor Figure 30-42. Receive Stati

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-69 Figure 30-43. Receive Globa

OverviewMPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 1-5 – Performing HEC error detection and single bit error correct

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-70 Freescale Semiconductor Table 30-32 describes free b

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-71 30.10.5.3 ATM Controller Buf

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-72 Freescale Semiconductor Table 30-35 describes AAL5 R

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-73 30.10.5.5 AAL1 RxBDFigure 30

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-74 Freescale Semiconductor 30.10.5.6 AAL0 RxBDFigure 30

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-75 30.10.5.7 AAL1 CES RxBDRefer

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-76 Freescale Semiconductor 30.10.5.9 AAL5, AAL1 CES Use

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-77 30.10.5.11 AAL1 TxBDsFigure

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 230-78 Freescale Semiconductor Table 30-39 describes AAL1 T

ATM Controller and AAL0, AAL1, and AAL5MPC8260 PowerQUICC II Family Reference Manual, Rev. 2Freescale Semiconductor 30-79 Table 30-40 describes AAL0 T