Freescale-semiconductor MCF5480 Manual do Utilizador descarregar pdf (Página 62)

MCF548x Reference Manual, Rev. 3

1-4 Freescale Semiconductor

— Memory management unit (MMU)

– Separate, 32-entry, fully-associative instruction and data translation lookahead buffers

— Floating point unit (FPU)

– Double-precision support that conforms to IEEE-754 standard

– Eight floating point registers

• Internal master bus (XLB) arbiter

— High performance split address and data transactions

— Support for various parking modes

• 32-bit double data rate (DDR) synchronous DRAM (SDRAM) controller

— 66–133 MHz operation

— Supports both DDR and SDR DRAM

— Built-in initialization and refresh

— Up to four chip selects enabling up to 1 GB of external memory

• Version 2.2 peripheral component interconnect (PCI) bus

— 32-bit target and initiator operation

— Support for up to five external PCI masters

— 33–66 MHz operation with PCI bus to XLB divider ratios of 1:1, 1:2, and 1:4

• Flexible multi-function external bus (FlexBus)

— Supports operation with the following:

– Non-multiplexed 32-bit address and 32-bit data (32-bit address muxed over

PCI bus–PCI not usable)

– Multiplexed 32-bit address and 32-bit data (PCI usable)

– Multiplexed 32-bit address and 16-bit data

– Multiplexed 32-bit address and 8-bit data

— Provides a glueless interface to boot Flash/ROM, SRAM, and peripheral devices

— Up to six chip selects

— 33–66 MHz operation

• Communications I/O subsystem

— Intelligent 16-channel DMA controller

— Dedicated DMA channels for receive and transmit on all subsystem peripheral interfaces

— Up to two 10/100 Mbps fast Ethernet controllers (FECs), each with separate 2-Kbyte receive

and transmit FIFOs

— Universal serial bus (USB) version 2.0 device controller

– Support for one control and six programmable endpoints — interrupt, bulk, or isochronous

– 4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM

– Integrated physical layer interface

— Up to four programmable serial controllers (PSCs) each with separate 512-byte receive and

transmit FIFOs for UART, USART, modem, codec, and IrDA 1.1 interfaces

—I

C peripheral interface

— Two FlexCAN controller area network 2.0B controllers each with 16 message buffers

— DMA serial peripheral interface (DSPI)

• Optional security encryption controller (SEC) module

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