Freescale-semiconductor MCF5480 Manual do Utilizador descarregar pdf (Página 71)

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 2-1

Chapter 2

Signal Descriptions

2.1 Introduction

This chapter describes the MCF548x signals.

NOTE

The terms ‘assertion’ and ‘negation’ are used to avoid confusion when

dealing with a mixture of active-low and active-high signals. The term

‘asserted’ indicates that a signal is active, independent of the voltage level.

The term ‘negated’ indicates that a signal is inactive.

Active-low signals, such as RAS and TA, are indicated with an overbar.

2.1.1 Block Diagram

Figure 2-1 displays the signals of the MCF548x.

1 2 ... 66 67 68 69 70 71 72 73 74 75 76 ... 102 103

MCF548x Reference Manual 1
How to Reach Us: 2
Contents 10
About This Book 41
Suggested Reading 43
Conventions 44
Acronyms and Abbreviations 45
SYNC_SEG 53
Chapter 1 59
Overview 59
1.2 MCF548x Block Diagram 60
1.3 MCF548x Family Products 61
1.4 MCF548x Family Features 61
1-4 Freescale Semiconductor 62
Freescale Semiconductor 1-5 63
1.4.2 Debug Module (BDM) 64
1.4.3 JTAG 64
1.4.4 On-Chip Memories 65
1.4.6.1 DMA Controller 66
1.4.6.5 I 67
C (Inter-Integrated Circuit) 67
1-10 Freescale Semiconductor 68
1.4.11.1 Timers 69
1.4.11.2 Interrupt Controller 70
1.4.11.3 General Purpose I/O 70
Chapter 2 71
Signal Descriptions 71
Figure 2-1. MCF548x Signals 72
C Serial data I/O 8 GPI 77
C Serial clock I/O 8 GPI 77
2.2 MCF548x External Signals 86
2.2.1.4 Read/Write (R/W) 87
2.2.1.5 Transfer Burst (TBST) 87
2.2.1.8 Output Enable (OE) 88
Freescale Semiconductor 2-19 89
2.2.3 PCI Controller Signals 90
Freescale Semiconductor 2-21 91
2.2.5 Clock and Reset Signals 92
2.2.7 Ethernet Module Signals 94
Freescale Semiconductor 2-25 95
2-26 Freescale Semiconductor 96
2.2.10 FlexCAN Signals 97
2.2.11 I 97
C I/O Signals 97
2.2.12 PSC Module Signals 98
2.2.14 Timer Module Signals 99
2.2.15 Debug Support Signals 99
2.2.16 Test Signals 100
Freescale Semiconductor 2-31 101
2-32 Freescale Semiconductor 102
Processor Core 103
Chapter 3 105
ColdFire Core 105
3.2.1 Enhanced Pipelines 106
Features 107
3-4 Freescale Semiconductor 108
3-6 Freescale Semiconductor 110
3.3 Programming Model 111
3.3.1 User Programming Model 113
3.3.3 EMAC Programming Model 114
3.3.4 FPU Programming Model 114
Programming Model 115
3.3.5.1 Status Register (SR) 116
3.3.6 Programming Model Table 117
3.4 Data Format Summary 119
Data Format Summary 121
3.5 Addressing Mode Summary 122
3.6 Instruction Set Summary 123
Instruction Set Summary 125
3.6.2 Instruction Set Summary 126
(EMAC) execute engine 138
31 28 27 26 25 18 17 16 15 0 142
3.8.2 Processor Exceptions 143
Privilege 144
3.9 Precise Faults 146
Freescale Semiconductor 3-43 147
3-44 Freescale Semiconductor 148
Chapter 4 149
4.1.1 MAC Overview 150
4.1.2 General Operation 150
=k()yi k–() b 150
Introduction 151
Figure 4-6. EMAC Register Set 153
4.2.2 Mask Register (MASK) 158
4.3.2 Data Representation 160
4.3.3 EMAC Opcodes 161
4-18 Freescale Semiconductor 166
Chapter 5 167
Memory Management Unit (MMU) 167
5-2 Freescale Semiconductor 168
5.2.3.1 Precise Faults 170
5.2.3.2 MMU Access 170
5.2.3.3 Virtual Mode 170
Freescale Semiconductor 5-5 171
5.4.1 Precise Faults 173
5.5 MMU Definition 175
5.5.2 MMU Functionality 176
5.5.3 MMU Organization 176
5.5.3.2 MMU Memory Map 177
Figure 5-5 shows the MMUOR 178
MMU Definition 179
5.5.4 MMU TLB 184
5.5.5 MMU Operation 185
5.6 MMU Implementation 186
Table 5-13. PLRU State Bits 187
5.6.3 TLB Locked Entries 188
5.7 MMU Instructions 189
5-24 Freescale Semiconductor 190
Chapter 6 191
Floating-Point Unit (FPU) 191
Figure 6-2. Mantissa 193
6.2.3.1 Normalized Numbers 194
6.2.3.2 Zeros 194
6.2.3.3 Infinities 194
3130 23 22 0 195
6362 52 51 0 195
6.3 Register Definition 197
Register Definition 199
6.4.1 Intermediate Result 201
6.4.2 Rounding the Result 202
Freescale Semiconductor 6-13 203
Table 6-6. Tie-Case Example 204
6.5.2 Conditional Testing 205
6.6 Floating-Point Exceptions 207
Program Counter Assignment 208
Freescale Semiconductor 6-19 209
6.6.1.4 Operand Error (OPERR) 211
6.6.1.5 Overflow (OVFL) 211
6.6.1.6 Underflow (UNFL) 212
6.6.1.7 Divide-by-Zero (DZ) 212
6.6.1.8 Inexact Result (INEX) 213
31 24 23 19 18 16 15 0 214
6.7 Instructions 215
Instructions 217
(Continued) 218
Chapter 7 221
Local Memory 221
7.4 SRAM Register Definition 222
7.3 SRAM Operation 222
SRAM Register Definition 223
7.5 SRAM Initialization 224
SRAM Initialization 225
7.6 Power Management 226
7.7 Cache Overview 226
7.8 Cache Organization 227
7.8.2 The Cache at Start-Up 228
Cache Organization 229
7.9 Cache Operation 230
Freescale Semiconductor 7-11 231
7.9.1 Caching Modes 232
Freescale Semiconductor 7-13 233
7.9.2 Cache Protocol 234
7.9.2.3 Read Hit 235
7.9.4.1 Cache Filling 235
7.9.4.2 Cache Pushes 236
7.9.5 Cache Locking 237
Cache Register Definition 239
7.11 Cache Management 243
31 13 12 4 3 0 244
Cache Management 245
7.12 Cache Operation Summary 246
Freescale Semiconductor 7-27 247
Cache Operation Summary 249
Chapter 8 251
Debug Support 251
8.2 Signal Descriptions 252
Figure 8-2. PSTCLK Timing 253
8.3 Real-Time Trace Support 255
Real-Time Trace Support 257
Table 8-5. 0xE Status Posting 258
WDMREG and RDMREG 260
GO command clear TRG 262
GO command clear HALT 262
GO command clear BKPT 262
WDMREG command 266
1514131211109876543210 270
RDMREG and WDMREG commands 272
8.5.1 CPU Halt 278
GO command clears CSR[26–24] 279
8.5.2 BDM Serial Interface 280
8.5.3 BDM Command Set 281
Background Debug Mode (BDM) 283
8-34 Freescale Semiconductor 284
/RDREG Command Sequence 285
/RDREG Command Format 285
/WDREG Command Sequence 286
/WDREG Command Format 286
Command Sequence: 287
WRITE Command Format 288
WRITE Command Sequence 289
15 12 11 8 7 4 3 0 290
FILL Command Format 291
8-42 Freescale Semiconductor 292
0x0 0xC 0x0 0x0 292
Freescale Semiconductor 8-43 293
0x00x00x00x0 293
NEXT CMD 294
“CMD COMPLETE” 294
FORCE_TA 295
15 12 11 8 7 5 4 0 300
8.6 Real-Time Debug Support 301
8-52 Freescale Semiconductor 302
8.6.1.1 Emulator Mode 303
8.7.1 User Instruction Set 304
8.8 ColdFire Debug History 311
8-62 Freescale Semiconductor 312
Freescale Semiconductor 8-63 313
System Integration Unit 315
Chapter 9 317
System Integration Unit (SIU) 317
Table 9-1. SIU Register Map 318
CPU can halt the DMA 319
151413121110987654321 0 320
Chapter 10 323
10.1.2 Clocking Overview 324
10.1.3 Internal Bus Overview 324
10.1.4 XL Bus Features 325
10.1.6.2 Address Pipelines 326
10.2 PLL 327
10.3 XL Bus Arbiter 328
10.3.2.2 Bus Grant Mechanism 329
10.3.2.3 Watchdog Functions 330
XL Bus Arbiter 331
Chapter 11 341
General Purpose Timers (GPT) 341
11.2 External Signals 342
1514131211109876543 2 1 0 347
11.4 Functional Description 348
Chapter 12 349
Slice Timers (SLT) 349
Chapter 13 353
Interrupt Controller 353
13.2.1 Register Descriptions 357
76543210 362
13.2.1.6.1 Interrupt Sources 364
Chapter 14 367
Edge Port Module (EPORT) 367
14.3.1 Memory Map 368
14.3.2 Register Descriptions 368
Chapter 15 373
15.1.1 Overview 374
15.2 External Pin Description 375
External Pin Description 377
15.3.1 Register Overview 379
15.3.2 Register Descriptions 380
PDDR_FBCS register 386
151413 1211109876543210 396
15.4 Functional Description 404
Freescale Semiconductor 15-33 405
15-34 Freescale Semiconductor 406
Part III 407
On-Chip Integration 407
Chapter 16 409
32-Kbyte System SRAM 409
16.1.2 Features 410
16.1.3 Overview 410
(TCCRDR) 413
(TCCRDW) 414
16.3 Functional Description 416
Chapter 17 417
17.2 Byte Lanes 418
17.3 Address Latch 418
17.4 External Signals 419
17-4 Freescale Semiconductor 420
17.4.8 Output Enable (OE) 421
17.5 Chip-Select Operation 422
17.5.2 Chip-Select Registers 423
Chip-Select Operation 425
151413121110987654 3 210 426
17.6 Functional Description 428
17.6.4 Bus Cycle Execution 429
Table 17-11. Bus Cycle States 430
17.6.5.1 Basic Read Bus Cycle 431
S0 S1 S2 S3 432
Functional Description 433
17.6.5.4 Timing Variations 437
S0 S1 WS S2 S3 439
S0 AS S1 S2 S3 440
S0 S1 S2 S3 AH 441
17.6.6 Burst Cycles 442
S0 S1 S2 S2 S2 S2 S3 443
S0 AS S1 S2 S2 S2 S2 S3 AH 446
17.6.7 Misaligned Operands 447
17.6.8 Bus Errors 448
Chapter 18 449
SDRAM Controller (SDRAMC) 449
18.2.3 Block Diagram 450
External Signal Description 451
18-4 Freescale Semiconductor 452
Interface Recommendations 453
18.4.2 SDRAM SDR Connections 454
18.5 SDRAM Overview 457
18.5.1.2 Read Command (READ) 458
Freescale Semiconductor 18-11 459
Figure 18-6. Mode Register 460
SDRAM Overview 461
18.5.2.1 SDR Initialization 462
18.5.2.2 DDR Initialization 462
18.6 Functional Overview 463
Table 18-6. SDRAMC Memory Map 464
151413121110987654 3 2 1 0 466
18.8 SDRAM Example 472
SDRAM Example 473
0111_0011_0110_0010 474
0100_0110_0111_0111 475
151413121110987 6 543210 476
18.8.8 Issue a PALL command 478
18.8.12 Initialization Code 482
18-36 Freescale Semiconductor 484
Chapter 19 485
PCI Bus Controller 485
Freescale Semiconductor 19-3 487
Table 19-2. PCI Memory Map 488
Header Type 494
PCIGSCR Field Descriptions 498
PCITBATR1 Field Descriptions 500
PCIIWCR Field Descriptions 504
PCICAR Field Descriptions 506
Table 19-18 507
Bits Name Description 508
19.4 Functional Description 532
19.4.1.3 PCI Transactions 533
012345678 534
19.4.1.4 PCI Bus Commands 535
19.4.1.5 Addressing 536
31 11 10 8 7 2 1 0 538
19.4.2 Initiator Arbitration 539
19.4.2.1 Priority Scheme 540
Freescale Semiconductor 19-57 541
19.4.4.1 Endian Translation 542
Transactions (Continued) 543
31 11 10 2 1 0 544
19-62 Freescale Semiconductor 546
19.4.5.2 Local Memory Writes 548
19.4.5.3 Data Translation 548
19.4.5.4 Target Abort 550
19.4.5.5 Latrule Disable 550
19.4.6.1 Access Width 551
19.4.6.2 Addressing 551
19.4.6.3 Data Translation 552
19.4.6.4 Initialization 552
19.4.6.5 Restart and Reset 552
19.4.6.6 PCI Commands 553
19.4.6.7 FIFO Considerations 553
19.4.6.8 Alarms 553
19.5 Application Information 554
19.5.2 Address Maps 555
19.5.2.1 Address Translation 556
Application Information 557
XL Bus Arbitration Priority 559
19-76 Freescale Semiconductor 560
Chapter 20 561
PCI Bus Arbiter Module 561
20.1.3 Features 562
20.2.1 Frame (PCIFRM) 562
20.2.3 PCI Clock (CLKIN) 562
20.3 Register Definition 563
20.4 Functional Description 565
20.4.2 Arbitration 566
20.4.2.3 Arbitration Latency 567
20.4.2.4 Arbitration Examples 567
20.4.3 Master Time-Out 569
20.5 Reset 570
20.6 Interrupts 570
Chapter 21 571
21.1.2 The CAN System 572
21.1.3 Features 573
21.1.4 Modes of Operation 573
21.1.4.3 Module Disabled Mode 574
21.1.4.4 Loop-Back Mode 574
21.1.4.5 Listen-Only Mode 574
21.2 External Signals 575
21.3.2 Register Descriptions 576
21.3.2.4 Rx Mask Registers 581
151141391211109876543210 588
21.4 Functional Overview 589
Functional Overview 591
21.4.3 Transmit Process 593
21.4.4 Arbitration Process 594
21.4.5 Receive Process 594
21.4.5.1 Self-Received Frames 595
21-26 Freescale Semiconductor 596
21.4.7.1 Remote Frames 597
21.4.8 Time Stamp 598
21.4.9 Bit Timing 598
x ≤ 127 600
21.5.1 Interrupts 601
21-32 Freescale Semiconductor 602
Chapter 22 603
22.3 Block Diagram 604
22.4 Overview 604
22.4.2 SEC Controller Unit 605
22.4.3 Crypto-Channels 605
22.4.4 Execution Units (EUs) 606
Table 22-3. SEC Register Map 610
Mnemonic Name Page 611
22.6 Controller 612
22.6.1 EU Access 613
22.6.2 Multiple EU Assignment 613
22.6.3 Multiple Channels 613
22.6.4 Controller Registers 613
Controller 615
22-14 Freescale Semiconductor 616
22.7 Channels 620
Freescale Semiconductor 22-19 621
Channels 623
22.7.1.4 Fetch Register (FRn) 629
22.8.1 AFEU Register Map 630
22.9.1 DEU Register Map 636
22.10.1 MDEU Register Map 642
Figure 22-31 645
22.11.1 RNG Register Map 648
RNG Execution Unit (RNG) 649
Figure 22-35 650
22.12.1 AESU Register Map 652
Figure 22-38 655
22.13 Descriptors 658
22.13.1.1 Descriptor Header 659
Table 22-39. Descriptor Types 661
31 16 15 0 662
22.13.2 Descriptor Chaining 663
Table 22-43. Descriptor Types 664
Descriptors 665
22.13.4 Descriptor Classes 666
22.13.4.2 Static Descriptors 667
— CETSED 674
— INT HMAC PD ALG 679
IM — CM ED 685
22.14.6.1 Snooping 693
Chapter 23 709
23.1.2 Features 710
23.1.3 Modes of Operation 710
23.3.1 Memory Map 712
23.3.2 Register Descriptions 712
23.3.2.3 Bypass Register 713
23.3.2.5 TEST_CTRL Register 713
23.4 Functional Description 714
23.4.3 JTAG Instructions 715
23.4.3.2 IDCODE Instruction 716
23.5.1 Restrictions 717
23-10 Freescale Semiconductor 718
Communications Subsystem 719
Chapter 24 721
Multichannel DMA 721
24.1.2 Overview 722
24.1.3 Features 722
24.2 External Signals 723
24.3.2 Memory Structure 724
24.3.3 DMA Registers 725
24.3.3.3 Current Pointer (CP) 727
24.3.3.4 End Pointer (EP) 728
24.3.3.6 PTD Control (PTD) 729
15141312111098 7 6 5 43210 731
24.3.3.16 PTD Debug Registers 739
24.4 Functional Description 742
24.4.2 Descriptors 743
24.4.3 Task Initialization 743
24.4.4 Initiators 743
24.4.5 Prioritization 744
24.4.6 Context Switch 744
24.4.7 Data Movement 744
24.4.8 Data Manipulation 744
24.4.8.1 LURC Features 745
24.4.9 Line Buffers 746
24.5 Programming Model 747
24.5.2 Task Memory 748
749
24.6 Timing Diagrams 750
24.6.3 Pipelined Requests 751
24-32 Freescale Semiconductor 752
Chapter 25 753
Comm Timer Module (CTM) 753
25.1.2 Overview 754
25.2.2 Register Descriptions 756
25.3 Functional Description 759
2 3 4 5 6 7 8 1 2 3 4 5 6 761
7 8 2 3 4 5 6 7 8 761
000001 000001 000001 761
25-10 Freescale Semiconductor 762
Chapter 26 763
26.2 Signal Description 764
26.2.4 PSCnTXD 765
26.3.1 Overview 765
26.3.2 Module Memory Map 765
Name Byte0 Byte1 Byte2 Byte3 766
26.3.3 Register Descriptions 767
76543210 Mode 769
15 14 13 12 11 1098 7 6543210 770
RCSEL TCSEL 773
26.3.3.12 Input Port (PSCIPn) 783
76543210Mode 784
Table 26-21. SIM[2:0] 785
Eqn. 26-1 788
Eqn. 26-2 789
15141312111098765432 1 0 790
26.4 Functional Description 797
26.4.2 Multidrop Mode 798
26.4.3 Modem8 Mode 799
26.4.4 Modem16 Mode 800
26.4.5 AC97 Mode 801
26.4.5.1 Transmitter 802
26.4.5.2 Receiver 802
26.4.5.3 Low Power Mode 802
26.4.6 SIR Mode 803
26.4.7 MIR Mode 803
26.4.8 FIR Mode 804
26.4.9 PSC FIFO System 805
26.4.9.1 RX FIFO 806
26.4.9.2 TX FIFO 807
26.4.10 Looping Modes 808
26.5 Resets 809
26.6 Interrupts 810
26.7 Software Environment 810
26.7.2 Configuration 811
26.7.2.2 Modem8 Mode 812
26.7.2.3 Modem16 Mode 813
26.7.2.4 AC97 Mode 813
26.7.2.5 SIR Mode 814
26.7.2.6 MIR Mode 815
26.7.2.7 FIR Mode 816
26.7.3 Programming 817
26.7.3.2 FIR Mode 818
Chapter 27 819
27.3 Block Diagram 820
27.4 Modes of Operation 820
27.5 Signal Description 821
27.6 Memory Map and Registers 822
Memory Map and Registers 823
DCTAR registers is used 826
27.7 Functional Description 836
27.7.2.1 Master Mode 838
27.7.2.2 Slave Mode 838
Freescale Semiconductor 27-21 839
27.7.4 Transfer Formats 843
12345678910111213141516 844
27-32 Freescale Semiconductor 850
27.8.1 How to Change Queues 851
27.8.2 Baud Rate Settings 851
27.8.3 Delay Settings 852
Table 27-23. Delay Values 853
Chapter 28 855
C Interface 855
28.2 External Signals 856
28.3.1 I 857
C Register Map 857
28.3.2 Register Descriptions 857
28.3.2.2 I 858
28.3.2.3 I 859
C Control Register (I2CR) 859
28.3.2.4 I 859
C Status Register (I2SR) 859
Figure 28-5. I 860
28.3.2.5 I 861
C Data I/O Register (I2DR) 861
28.3.2.6 I 861
28.4 Functional Description 862
28.4.1 START Signal 863
28.4.3 STOP Signal 863
28.4.4 Data Transfer 863
28.4.5 Acknowledge 864
28.4.6 Repeated Start 865
28.5 Initialization Sequence 866
Initialization Sequence 867
28.5.3 Generation of STOP 869
28.5.5 Slave Mode 870
28.5.6 Arbitration Lost 872
28.5.7 Flow Control 872
C Interrupt Routine 873
28-20 Freescale Semiconductor 874
Chapter 29 875
USB 2.0 Device Controller 875
29.1.3 Block Diagram 876
29.1.3.3 FIFO Controller 877
29.1.3.4 FIFO RAM Manager 877
29.2.1 USB Memory Map 878
15 14131211109876543210 886
29.2.3 USB Counter Registers 897
EPnINACR) 901
EPnINMPSR) 902
29.3 Functional Description 921
29.4 Software Interface 921
29-48 Freescale Semiconductor 922
29.4.1.3 Endpoint Registers 923
29.4.2 Exception Handling 924
29.4.3.1 USB Packets 925
29.4.3.2 Sending Packets 925
29.4.3.3 Receiving Packets 925
29.4.3.4 USB Transfers 926
29.4.3.5 Control Transfers 927
29.4.3.6 Bulk Traffic 928
29.4.3.7 Interrupt Traffic 928
Freescale Semiconductor 29-55 929
29-56 Freescale Semiconductor 930
Chapter 30 931
30.1.3 Overview 932
30.1.4 Features 933
30.1.5 Modes of Operation 933
30.2 External Signals 934
Freescale Semiconductor 30-5 935
Table 30-4. Module Memory Map 936
Register (EIR) 941
Register (EIMR) 943
15 14 131211109876543210 947
FECTFSR[ALARM] bit is set 969
30.4 Functional Description 973
30.4.4 FEC Frame Transmission 976
30.4.5 FEC Frame Reception 977
30-48 Freescale Semiconductor 978
30.4.7 Hash Algorithm 979
Eqn. 30-1 980
30.4.10 Collision Handling 983
30.4.12.1 Transmission Errors 984
30.4.13 MII Data Frame 985
30-58 Freescale Semiconductor 988
Mechanical 989
Chapter 31 991
Mechanical Data 991
Pinout 993
31.3 Mechanical Diagrams 998
PBGA package 1000
31.6 Case Drawing 1010
Appendix A 1011
MCF548x Memory Map 1011
A-4 Freescale Semiconductor 1014

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