Freescale-semiconductor ColdFire MCF52210 Manual do Utilizador descarregar pdf (Página 45)

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101

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor 3-1

Chapter 3

ColdFire Core

3.1 Introduction

This section describes the organization of the Version 2 (V2) ColdFire

processor core and an overview

of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the

ColdFire Family Programmer’s Reference Manual.

3.1.1 Overview

As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an

instruction buffer.

Figure 3-1. V2 ColdFire Core Pipelines

The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched

instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the

Instruction

FIFO

Decode & Select,

Address

IAG

DSOC

AGEX

Instruction Buffer

Address

Generation

Fetch Cycle

Generation,

Execute

Operand Fetch

Instruction

Operand

Pipeline

Execution

Fetch

Pipeline

Address [31:0]

Read Data[31:0]

Write Data[31:0]

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Freescale-semiconductor ColdFire MCF52210 Manual do Utilizador Página 45

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