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DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2

Freescale Semiconductor C-1

Appendix C Programmer’s Reference

C.1 Introduction

This section has been compiled as a reference for programmers. It contains a table showing the addresses

of all the DSPs memory-mapped peripherals, an interrupt address table, an interrupt exception priority

table, a quick reference to the host interface, and programming sheets for the major programmable

registers on the DSP.

C.1.1 Peripheral Addresses

Table C-1 lists the memory addresses of all on-chip peripherals.

C.1.2 Interrupt Addresses

Table C-2 lists the interrupt starting addresses and sources.

C.1.3 Interrupt Priorities

Table C-3 lists the priorities of specific interrupts within interrupt priority levels.

Table C-1. Internal I/O Memory Map

Peripheral Address Register Name

IPR $FFFFFF INTERRUPT PRIORITY REGISTER CORE (IPR-C)

$FFFFFE INTERRUPT PRIORITY REGISTER PERIPHERAL (IPR-P)

PLL $FFFFFD PLL CONTROL REGISTER (PCTL)

ONCE $FFFFFC ONCE GDB REGISTER (OGDB)

BIU $FFFFFB BUS CONTROL REGISTER (BCR)

$FFFFFA DRAM CONTROL REGISTER (DCR)

$FFFFF9 ADDRESS ATTRIBUTE REGISTER 0 (AAR0)

$FFFFF8 ADDRESS ATTRIBUTE REGISTER 1 (AAR1)

$FFFFF7 ADDRESS ATTRIBUTE REGISTER 2 (AAR2)

$FFFFF6 ADDRESS ATTRIBUTE REGISTER 3 (AAR3)

$FFFFF5 ID REGISTER (IDR)

1 2 ... 152 153 154 155 156 157 158 159 160 161 162 ... 183 184

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