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ESAI Programming Model

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2

6-24 Freescale Semiconductor

The ESAI frame sync generator functional diagram is shown in Figure 6-4.

6.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-17

The RFP3–RFP0 bits control the divide ratio of the receiver high frequency clock to the receiver serial bit

clock when the source of the receiver high frequency clock and the bit clock is the internal DSP clock.

When the HCKR input is being driven from an external high frequency clock, the RFP3-RFP0 bits specify

an additional division ration in the clock divider chain. See Table 6-6 for the specification of the divide

ratio. The ESAI high frequency generator functional diagram is shown in Figure 6-3.

6.3.3.5 RCCR Receiver Clock Polarity (RCKP) - Bit 18

The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked

out and latched in. If RCKP is cleared the data and the frame sync are clocked out on the rising edge of the

receive bit clock and the frame sync is latched in on the falling edge of the receive bit clock. If RCKP is

set the falling edge of the receive clock is used to clock the data and frame sync out and the rising edge of

the receive clock is used to latch the frame sync in.

6.3.3.6 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19

The Receiver Frame Sync Polarity (RFSP) determines the polarity of the receive frame sync signal. When

RFSP is cleared the frame sync signal polarity is positive (i.e the frame start is indicated by a high level

on the frame sync pin). When RFSP is set the frame sync signal polarity is negative (i.e the frame start is

indicated by a low level on the frame sync pin).

6.3.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20

The Receiver High Frequency Clock Polarity (RHCKP) bit controls on which bit clock edge data and

frame sync are clocked out and latched in. If RHCKP is cleared the data and the frame sync are clocked

out on the rising edge of the receive bit clock and the frame sync is latched in on the falling edge of the

receive bit clock. If RHCKP is set the falling edge of the receive clock is used to clock the data and frame

sync out and the rising edge of the receive clock is used to latch the frame sync in.

Table 6-6 Receiver High Frequency Clock Divider

RFP3-RFP0 Divide Ratio

$0 1

$1 2

$2 3

$3 4

... ...

$F 16

1 2 ... 83 84 85 86 87 88 89 90 91 92 93 ... 183 184

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