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Register Descriptions
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 71
Preliminary
5.6.12 Fast Interrupt 0 Match Register (FIM0)
Figure 5-14 Fast Interrupt 0 Match Register (FIM0)
5.6.12.1 Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; see Section 5.3.3 for details. IRQs used as fast interrupts must be set to priority level 2. Unexpected
results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become
the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being
declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector
number of each IRQ, refer to Table 4-3.
5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.6.14.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Base + $B
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0
FAST INTERRUPT 0
Write
RESET
0000000000000000
Base + $C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
FAST INTERRUPT 0 VECTOR ADDRESS LOW
Write
RESET
0000000000000000
Base + $D
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0 0 0
FAST INTERRUPT 0 VECTOR
ADDRESS HIGH
Write
RESET
0000000000000000
- 56F8322/56F8122 1
- Document Revision History 2
- IPBus Bridge (IPBB) 3
- Table of Contents 4
- Part 1 Overview 5
- 8KB of Data Flash 6
- 8KB of Data RAM 6
- 8KB of Boot Flash 6
- 1.2 Device Description 7
- 1.2.2 56F8122 Features 8
- Freescale Semiconductor 9 9
- 16 bits 10
- To/From IPBus Bridge 11
- Table 1-2 Bus Signal Names 12
- 1.5 Product Documentation 13
- 1.6 Data Sheet Conventions 13
- 2.1 Introduction 14
- Freescale Semiconductor 15 15
- 16 Freescale Semiconductor 16
- 2.2 Signal Pins 17
- Signal Pins 19
- 3.1 Introduction 26
- 3.2.3 External Clock Source 27
- 28 Freescale Semiconductor 28
- 3.5 Registers 29
- Part 4 Memory Map 30
- 4.3 Interrupt Vector Table 31
- (Continued) 32
- 4.4 Data Map 34
- 4.5 Flash Memory Map 34
- Flash Memory Map 35
- 4.6 EOnCE Memory Map 36
- (TMRA_BASE = $00 F040) 37
- (TMRC_BASE = $00 F0C0) 39
- (PWMA_BASE = $00 F140) 40
- (DEC0_BASE = $00 F180) 41
- (ITCN_BASE = $00 F1A0) 41
- (ADCA_BASE = $00 F200) 42
- Register Description 44
- (FM_BASE = $00 F400) 47
- (FC_BASE = $00 F800) 47
- 5.1 Introduction 52
- 5.2 Features 52
- 5.3 Functional Description 52
- Functional Description 53
- 5.4 Block Diagram 54
- 5.5 Operating Modes 54
- 5.6 Register Descriptions 55
- 56 Freescale Semiconductor 56
- Freescale Semiconductor 57 57
- 58 Freescale Semiconductor 58
- Freescale Semiconductor 59 59
- 60 Freescale Semiconductor 60
- Freescale Semiconductor 61 61
- 62 Freescale Semiconductor 62
- Bits 11–10 63
- 64 Freescale Semiconductor 64
- Freescale Semiconductor 65 65
- Bits 15–14 66
- 5.6.8.2 Reserved—Bits 13–6 66
- Freescale Semiconductor 67 67
- 68 Freescale Semiconductor 68
- Freescale Semiconductor 69 69
- 70 Freescale Semiconductor 70
- 5.6.12.1 Reserved—Bits 15–7 71
- 5.6.14.1 Reserved—Bits 15–5 71
- 5.6.15.1 Reserved—Bits 15–7 72
- 5.6.17.1 Reserved—Bits 15–5 73
- 5.6.18.2 Reserved—Bit 0 73
- 74 Freescale Semiconductor 74
- Freescale Semiconductor 75 75
- 76 Freescale Semiconductor 76
- 5.7 Resets 77
- 6.1 Introduction 77
- 6.2 Features 78
- 6.3 Operating Modes 78
- 6.4 Operating Mode Register 79
- 6.5 Register Descriptions 79
- 6.5.1.1 Reserved—Bits 15–6 80
- Freescale Semiconductor 81 81
- 6.5.2.6 Reserved—Bits 1–0 82
- 6.5.6.1 Reserved—Bits 15–12 83
- 6.5.6.2 RESET—Bit 11 83
- Figure 3-4) 84
- 6.5.7.5 HOME0 (HOME)—Bit 6 85
- 6.5.8.1 Reserved—Bits 15–8 86
- 6.5.8.2 GPIO C6 (C6)—Bit 7 86
- 6.5.8.3 GPIOC5 (C5)—Bit 6 86
- Freescale Semiconductor 87 87
- 88 Freescale Semiconductor 88
- Freescale Semiconductor 89 89
- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 90
- ISAL[23:22] 90
- 111111 1 11111 1 1 11 90
- ISAL[21:6] 90
- 6.7 Power-Down Modes 91
- 6.9 Resets 92
- Part 7 Security Features 93
- 7.2.3 Flash Lockout Recovery 94
- << 95
- 8.1 Introduction 96
- 8.2 Configuration 96
- Configuration 97
- 8.3 Memory Maps 98
- 9.1 JTAG Information 98
- Part 10 Specifications 99
- Comments Symbol 101
- Unit Notes 101
- 1. No Output Switching 105
- Table 10-10. PLL Parameters 106
- 10.2.2 Temperature Sense 107
- Figure 10-2 Signal States 108
- External 109
- 10.7 Oscillator Parameters 110
- Oscillator Parameters 111
- First Fetch 113
- Not IRQA Interrupt Vector 114
- First Instruction Fetch 114
- Table 10-18 SPI Timing 115
- 10.10 Quad Timer Timing 118
- Figure 10-15 RXD Pulse Width 119
- Figure 10-16 TXD Pulse Width 119
- Table 10-21 SCI Timing 119
- 10.14 JTAG Timing 120
- JTAG Timing 121
- Table 10-24 ADC Parameters 122
- 124 Freescale Semiconductor 124
- Preliminary 124
- 10.17 Power Consumption 125
- • Cload is expressed in pF 126
- Freescale 127
- Freescale Semiconductor 131 131
- 132 Freescale Semiconductor 132
- Freescale Semiconductor 133 133
- DDA_OSC_PLL 134
- Part 13 Ordering Information 135
- How to Reach Us: 136
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