Freescale-semiconductor StarCore SC140 Manual do Utilizador descarregar pdf (Página 115)

Overview of the Combined JTAG and EOnCE Interface

SC140 DSP Core Reference Manual 4-5

Figure 4-2. TAP Controller State Machine

At power-up or during normal operation of the host, the TAP is forced into the Test-Logic-Reset state

TMS signal is driven high for five or more Test Clock (TCK) cycles.

When test access is required,

TMS is set low to cause the TAP to exit the Test-Logic-Reset and move

through the appropriate states. From the Run-Test/Idle state, an instruction register scan or a data register

scan can be issued to transition through the appropriate states.

Table 4-3. JTAG Scan Paths

Select-DR Scan Path Select-IR Scan Path

Select-DR_SCAN Select-IR_SCAN

Capture-DR Capture-IR

Shift-DR Shift-IR

Exit1-DR Exit1-IR

Update-DR Update-IR

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

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