Freescale-semiconductor StarCore SC140 Manual do Utilizador descarregar pdf (Página 198)

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5-18 SC140 DSP Core Reference Manual

Instruction Timing

Table 5-7. Loop Change-Of-Flow Instructions

5.3.2.1 Direct, PC-Relative, and Conditional COF

The SC140 core implements a five-stage pipeline with two stages dedicated to memory access. This results

in the addition of two clock cycles for unconditional COF instructions that use immediate values as well as

the addition of three clock cycles for the PC-relative COF instructions. Conditional change-of-flow

instructions, where the condition is true (meaning the change-of-flow operation is taken), always take an

additional three cycles. When a conditional change-of-flow is determined as not taken (meaning the

condition is false), there are no additional cycles.

JMPD Jump (delayed)

JSR Jump to subroutine

JSRD Jump to subroutine (delayed)

JT Jump if true

JTD Jump if true (delayed)

RTE Return from exception

RTED Return from exception (delayed)

RTS Return from subroutine

RTSD Return from subroutine (delayed)

RTSTK Restore PC from the stack, updating SP

RTSTKD Restore PC from the stack, updating SP (delayed)

TRAP Execute a precise software exception

Instruction Description

BREAK Terminate the loop and branch to an address

CONT Jump to the start of the loop to start the next iteration

CONTD Jump to the start of the loop to start the next iteration (delayed)

SKIPLS Test the active LC and skip the loop if it is equal or smaller than zero

Table 5-6. Non-Loop Change-of-Flow Instructions (Continued)

Instruction Description

1 2 ... 193 194 195 196 197 198 199 200 201 202 203 ... 759 760

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