Freescale-semiconductor StarCore SC140 Manual do Utilizador descarregar pdf (Página 320)

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A-6 SC140 DSP Core Reference Manual

DSP Core Instruction Set

A.1.3 Data Representation in Memory for the Examples

For the examples in this appendix, the convention for the representation of data in memory is to show the

same order in memory as is in the source register for a write. For example, a 32-bit write from a register

containing $12345678 to address $100 will be shown as: ($100) = $12345678. The exact order of

multi-byte operands in memory depends on the endian mode, and is described in Section 2.4.1, “SC140

Endian Support,” on page 2-56.

A.1.4 Encoding Notation

The instruction encoding is defined for each instruction under Instruction Formats and Opcodes and

Instruction Fields. Each instruction field may not be contiguous in the opcode, but the order of the bits in

each field is consistent from the opcode to the definition of the field. For example, in the MOVE.B

instruction, the encoding for the opcode is

The order of bits for a16 (AAA---A) is the MSB in the first bit at the left-most position in word 1. The LSB

is the right-most position in word 2. If written out fully, the encoding would be:

A more complicated example is for BSR, where two fields are intermixed. The order for each field is

maintained, monotonically decreasing from left to right.

The definition for the field is

If the field was written out in the encoding table, it would appear as follows:

15 8 7 0

MOVE.B (a16),DR 0001HHHHAAA01110

100AAAAAAAAAAAAA

15 8 7 0

MOVE.B (a16),DR 0001HHHHA15A14A1301110

1 0 0A12A11A10A9A8A7A6A5A4A3A2A1A0

BSR >label 0010a011AAA11aaa

100AAAAAAAAAAAAa

displacement

(>label)

aaaaaAAAAAAAAAAAAAAA0 20-bit signed PC relative displacement

BSR >label 0010a20011A15A14A1311a19a18a17

1 0 0A12A11A10A9A8A7A6A5A4A3A2A1a16

1 2 ... 315 316 317 318 319 320 321 322 323 324 325 ... 759 760

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