Freescale-semiconductor StarCore SC140 Manual do Utilizador descarregar pdf (Página 185)

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Instruction Grouping

SC140 DSP Core Reference Manual 5-5

5.1.1.4 Execution

During the execution stage, all DALU arithmetic calculations are performed by:

• Reading the data operands from source registers

• Performing arithmetic operations on the data

• Writing the results to destination registers

5.2 Instruction Grouping

The SC140 instruction set architecture is built around a 16-bit instruction set for optimal code density and

performance. The core contains two AAUs and four ALUs that enable two instructions to the AAUs and

four instructions to the ALUs per clock cycle. The grouping of these instructions is specified explicitly in

the assembly source code and encoded by the assembler, subject to the encoding rules described later in

this section.

Example 5-1 shows an execution set containing the following four SC140 instructions: a MAC, an AND, a

memory read, and an AAU calculation. All four instructions execute independently in a single cycle.

Example 5-1. Four SC140 Instructions in an Execution Set

In the execution set above, the four SC140 instructions are grouped. When executed, the following occurs:

1. The contents of the D0 and D1 registers are multiplied fractionally. The result is subtracted

from the D7 data register. The final result is then rounded and stored in the D7 data register.

2. The contents of the D4 and D5 registers are ANDed together. The result is stored in the

D5 data register.

3. The contents of the 32-bit memory location (pointed to by the R0 register) are moved into

the R6 register.

4. The address in the R0 register is incremented by the contents of the N0 register.

5. The contents of R2 are added to the R3 register. This result is stored back in the R3 register.

A second case is illustrated in Example 5-2, which shows a six-instruction execution set that executes in

one clock cycle.

Example 5-2. Grouping Six SC140 Instructions in an Execution Set

DALU Instr

MACR -D0,D1,D7

ADDA R2,R3

AGU Instr

AND D4,D5 MOVE.L (R0)+N0,R6

AGU Instr

AGU

MOVE.W(R0)+N3,D2

DALU

MACR D0,D2,D5

DALU

MAC D3,D4,D6

DALU

ADR D3,D4

DALU

MAC D0,D1,D7

AGU

MOVE.L D0,R1

Instr Instr

Instr

1 2 ... 180 181 182 183 184 185 186 187 188 189 190 ... 759 760

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